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(unknown [IPv6:240e:358:11d1:f200:dc73:854d:832e:8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 33D1E66D47; Sat, 13 Apr 2024 00:41:46 -0400 (EDT) From: Xi Ruoyao To: Dave Hansen , Michael Kelley , Pawan Gupta Cc: Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org, Xi Ruoyao , Sean Christopherson , Andrew Cooper Subject: [PATCH v8 2/2] x86/mm: Don't disable PCID if the kernel is running on a hypervisor Date: Sat, 13 Apr 2024 12:41:29 +0800 Message-ID: <20240413044129.52812-2-xry111@xry111.site> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240413044129.52812-1-xry111@xry111.site> References: <20240413044129.52812-1-xry111@xry111.site> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Intel erratum for "incomplete Global INVLPG flushes" says: This erratum does not apply in VMX non-root operation. It applies only when PCIDs are enabled and either in VMX root operation or outside VMX operation. So if the kernel is running in a hypervisor, we are in VMX non-root operation and we should be safe to use PCID. Cc: Dave Hansen Cc: Michael Kelley Cc: Pawan Gupta Cc: Sean Christopherson Cc: Andrew Cooper Link: https://lore.kernel.org/all/168436059559.404.13934972543631851306.tip-bot2@tip-bot2/ Link: https://cdrdv2.intel.com/v1/dl/getContent/740518 # RPL042, rev. 13 Link: https://cdrdv2.intel.com/v1/dl/getContent/682436 # ADL063, rev. 24 Signed-off-by: Xi Ruoyao --- arch/x86/mm/init.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index c318cdc35467..6010f86c5acd 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -275,6 +275,14 @@ static void __init probe_page_size_mask(void) * microcode is not updated to fix the issue. */ static const struct x86_cpu_id invlpg_miss_ids[] = { + /* Only bare-metal is affected. PCIDs in guests are OK. */ + { + .vendor = X86_VENDOR_INTEL, + .family = 6, + .model = INTEL_FAM6_ANY, + .feature = X86_FEATURE_HYPERVISOR, + .driver_data = 0, + }, INTEL_MATCH(INTEL_FAM6_ALDERLAKE, 0x2e), INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L, 0x42c), INTEL_MATCH(INTEL_FAM6_ATOM_GRACEMONT, 0x11), -- 2.44.0