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Sat, 13 Apr 2024 10:58:49 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 667F63D97D; Sat, 13 Apr 2024 10:58:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MrZKCUC6" Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7075E2110B; Sat, 13 Apr 2024 10:58:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713005921; cv=none; b=I66Ah6IL67OLD8vuFifhYnUzU2+6UuC8EjmwcQiVL2kjx+Lx5efuV7TDE/ReASBdcrKB4WbsE9rmvFk+luERlsa0yICwEHo+mrSVUdGJivPxOsJA0gP+xMDU4e52bJuFJI5Ub0iG8Ye42tp1Ul5CzF/cObgizwkEbUrpXZqyyb0= ARC-Message-Signature:i=1; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/04/2024 09:21, Fabio Aiuto wrote: > Dear Krzysztof, > > Il Thu, Apr 11, 2024 at 09:52:12PM +0200, Krzysztof Kozlowski ha scritto: >> On 11/04/2024 18:58, Fabio Aiuto wrote: >>> Add property to trigger warm reset on PMIC_RST_B assertion >>> >> >> That's rather vague and does not tell me much why this is supposed to be >> board level configuration. It sounds more like a debugging feature: >> during development you want to retain memory contents for pstore etc. >> Then I could imagine this should be turned runtime, e.g. via >> sysfs/debugfs, because for example you want to start inspecting a >> customer's device. > > thanks, I spent too few time writing this commit log and I apologize > for that. I was thinking about something like: > > The default configuration of the PMIC behavior makes the PMIC > power cycle most regulators on PMIC_RST_B assertion. This power > cycling causes the memory contents of OCRAM to be lost. > Some systems needs some memory that survives reset and > reboot, therefore add a property to tell PMIC_RST_B is > wired. > > The actual configuration is made at probe time, anyway we need > to override the default behavior of the pmic to get a warm reset > everytime the PMIC_RST_B pin is asserted and this property tells > us that "something is wired to that pin" and "it has to behave > that way on pin assertion". Our use cases do not meet the need > of further runtime configuration change. What is the use case? Sorry, you did not bring any further argument why this is board specific. And please don't explain how probing works, but address the problem here: why type of reset is specific to board design. To me it is OS policy. Best regards, Krzysztof