Received-SPF: pass (google.com: domain of linux-kernel+bounces-143943-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223;
Precedence: bulk
MIME-Version: 1.0
References: <20240407123829.36474-1-cuiyunhui@bytedance.com>
 <abd135fa-c432-4e37-9792-07a0e17e93d5@arm.com> <CAEEQ3w=+C2J0ZS227-1P-B+pe_NRp_3i4c4CxGssiKqbpXx_qw@mail.gmail.com>
 <2cde00c8-7878-45c0-8621-fca4e70c75e7@arm.com> <ZhlcYRolZwm7UwJu@bogus> <Zhlg67dbl_S1GD0u@bogus>
In-Reply-To: <Zhlg67dbl_S1GD0u@bogus>
From: yunhui cui <cuiyunhui@bytedance.com>
Date: Sun, 14 Apr 2024 10:40:34 +0800
Message-ID: <CAEEQ3w=VrQRammHcKBhT=YGPTZ=ktK9PDhLCBM9ODpYMJw_=-Q@mail.gmail.com>
Subject: Re: [External] Re: [PATCH 1/2] ACPI: PPTT: Populate cacheinfo
 entirely with PPTT
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: Jeremy Linton <jeremy.linton@arm.com>, rafael@kernel.org, lenb@kernel.org, 
	linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, 
	paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, 
	linux-riscv@lists.infradead.org
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

Hi Sudeep=EF=BC=8CJeremy=EF=BC=8C

On Sat, Apr 13, 2024 at 12:27=E2=80=AFAM Sudeep Holla <sudeep.holla@arm.com=
> wrote:
>
> On Fri, Apr 12, 2024 at 05:08:01PM +0100, Sudeep Holla wrote:
> > diff --git i/arch/riscv/kernel/cacheinfo.c w/arch/riscv/kernel/cacheinf=
o.c
> > index 09e9b88110d1..92ab73ed5234 100644
> > --- i/arch/riscv/kernel/cacheinfo.c
> > +++ w/arch/riscv/kernel/cacheinfo.c
> > @@ -79,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> >         struct device_node *prev =3D NULL;
> >         int levels =3D 1, level =3D 1;
> >
> > +       if (!acpi_disabled) {
> > +               int ret, fw_levels, split_levels;
> > +
> > +               ret =3D acpi_get_cache_info(cpu, &fw_levels, &split_lev=
els);
> > +               if (ret)
> > +                       return ret;
> > +
> > +               /* must be set, so we can drop num_leaves assignment be=
low */
> > +               this_cpu_ci->num_leaves =3D fw_levels + split_levels;
> > +
> > +               for (idx =3D 0; level <=3D this_cpu_ci->num_levels &&
> > +                    idx < this_cpu_ci->num_leaves; idx++, level++) {
> > +                       if (level <=3D split_levels) {
> > +                               ci_leaf_init(this_leaf++, CACHE_TYPE_DA=
TA, level);
> > +                               ci_leaf_init(this_leaf++, CACHE_TYPE_IN=
ST, level);
> > +                       } else {
> > +                               ci_leaf_init(this_leaf++, CACHE_TYPE_UN=
IFIED, level);
> > +                       }
> > +               }
>
> Ofcourse we need to add here,
>                 return 0;
>
> > +       }
> > +
> >         if (of_property_read_bool(np, "cache-size"))
> >                 ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level=
);
> >         if (of_property_read_bool(np, "i-cache-size"))
> >
>
> --
> Regards,
> Sudeep

With this modification, I tested that I can obtain cacheinfo
correctly. If RISC-V later adds a new register describing the cache,
then we can continue to improve it in populate_cache_leaves().
Thank you for your comments and I will add you as Suggested-by in v2.

Thanks,
Yunhui