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[193.226.6.226]) by smtp.gmail.com with ESMTPSA id n22-20020aa7c796000000b0056feeb85ed0sm3451030eds.19.2024.04.14.13.14.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 14 Apr 2024 13:14:30 -0700 (PDT) Message-ID: Date: Sun, 14 Apr 2024 23:14:28 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 5/5] iio: adc: ad7192: Add AD7194 support To: David Lechner Cc: michael.hennerich@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alexandru.tachici@analog.com, lars@metafoo.de, jic23@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, andy@kernel.org, nuno.sa@analog.com, marcelo.schmitt@analog.com, bigunclemax@gmail.com, okan.sahin@analog.com, fr0st61te@gmail.com, alisa.roman@analog.com, marcus.folkesson@gmail.com, schnelle@linux.ibm.com, liambeguin@gmail.com References: <20240413151152.165682-1-alisa.roman@analog.com> <20240413151152.165682-6-alisa.roman@analog.com> Content-Language: en-US From: Alisa-Dariana Roman In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 13.04.2024 23:05, David Lechner wrote: > On Sat, Apr 13, 2024 at 10:13 AM Alisa-Dariana Roman > wrote: >> >> Unlike the other AD719Xs, AD7194 has configurable differential >> channels. The user can dynamically configure them in the devicetree. >> >> Also modify config AD7192 description for better scaling. >> >> Moved ad7192_chip_info struct definition to allow use of callback >> function parse_channels(). > > It looks like this no longer needs to be moved in this revision. > >> >> Signed-off-by: Alisa-Dariana Roman >> --- >> drivers/iio/adc/Kconfig | 11 ++- >> drivers/iio/adc/ad7192.c | 140 ++++++++++++++++++++++++++++++++++++--- >> 2 files changed, 138 insertions(+), 13 deletions(-) .. > >> + if (!ad7194_channels) >> + return -ENOMEM; >> + >> + indio_dev->channels = ad7194_channels; >> + indio_dev->num_channels = num_channels; >> + >> + device_for_each_child_node(dev, child) { >> + *ad7194_channels = ad7194_chan_diff; >> + ad7194_channels->scan_index = index++; >> + ret = ad7192_parse_channel(child, ad7194_channels); >> + if (ret) { >> + fwnode_handle_put(child); >> + return ret; >> + } >> + ad7194_channels++; >> + } >> + >> + *ad7194_channels = ad7194_chan_temp; >> + ad7194_channels->scan_index = index++; >> + ad7194_channels->address = AD7194_CH_TEMP; >> + ad7194_channels++; > > nit: It would seem more natural to have all voltage channels > altogether rather than having the temperature channel in between. I wrote the channels like this to match the other chips: static const struct iio_chan_spec ad7193_channels[] = { AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M), AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M), AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M), AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M), AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP), AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M), AD7193_CHANNEL(6, 1, AD7193_CH_AIN1), AD7193_CHANNEL(7, 2, AD7193_CH_AIN2), AD7193_CHANNEL(8, 3, AD7193_CH_AIN3), AD7193_CHANNEL(9, 4, AD7193_CH_AIN4), AD7193_CHANNEL(10, 5, AD7193_CH_AIN5), AD7193_CHANNEL(11, 6, AD7193_CH_AIN6), AD7193_CHANNEL(12, 7, AD7193_CH_AIN7), AD7193_CHANNEL(13, 8, AD7193_CH_AIN8), IIO_CHAN_SOFT_TIMESTAMP(14), }; Kind regards, Alisa-Dariana Roman