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From: "Zhang, Tina" <tina.zhang@intel.com>
To: Lu Baolu <baolu.lu@linux.intel.com>, "iommu@lists.linux.dev"
	<iommu@lists.linux.dev>
CC: "Tian, Kevin" <kevin.tian@intel.com>, "Liu, Yi L" <yi.l.liu@intel.com>,
	Jacob Pan <jacob.jun.pan@linux.intel.com>, Joerg Roedel <joro@8bytes.org>,
	Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v3 1/1] iommu/vt-d: Remove caching mode check before
 device TLB flush
Thread-Topic: [PATCH v3 1/1] iommu/vt-d: Remove caching mode check before
 device TLB flush
Thread-Index: AQHajtXXl0hn1tuKek2BkzH8BIG/FbFoks/A
Date: Mon, 15 Apr 2024 02:22:26 +0000
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References: <20240415013835.9527-1-baolu.lu@linux.intel.com>
In-Reply-To: <20240415013835.9527-1-baolu.lu@linux.intel.com>
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> -----Original Message-----
> From: Lu Baolu <baolu.lu@linux.intel.com>
> Sent: Monday, April 15, 2024 9:39 AM
> To: iommu@lists.linux.dev
> Cc: Tian, Kevin <kevin.tian@intel.com>; Liu, Yi L <yi.l.liu@intel.com>; J=
acob
> Pan <jacob.jun.pan@linux.intel.com>; Joerg Roedel <joro@8bytes.org>; Will
> Deacon <will@kernel.org>; Robin Murphy <robin.murphy@arm.com>; linux-
> kernel@vger.kernel.org; Lu Baolu <baolu.lu@linux.intel.com>
> Subject: [PATCH v3 1/1] iommu/vt-d: Remove caching mode check before
> device TLB flush
>=20
> The Caching Mode (CM) of the Intel IOMMU indicates if the hardware
> implementation caches not-present or erroneous translation-structure entr=
ies
> except for the first-stage translation. The caching mode is irrelevant to=
 the
> device TLB, therefore there is no need to check it before a device TLB
> invalidation operation.
>=20
> Remove two caching mode checks before device TLB invalidation in the driv=
er.
> The removal of these checks doesn't change the driver's behavior in criti=
cal
> map/unmap paths. Hence, there is no functionality or performance impact,
> especially since commit <29b32839725f> ("iommu/vt-d:
> Do not use flush-queue when caching-mode is on") has already disabled
> flush-queue for caching mode. Therefore, caching mode will never call
> intel_flush_iotlb_all().
The current logic is if the caching mode is being used and a domain isn't u=
sing first level I/O page table, then flush-queue won't be used. Otherwise,=
 the flush-queue can be enabled.
See https://github.com/torvalds/linux/commit/257ec29074

In other words, if the caching mode is being used and a domain is using fir=
st level I/O page table, the flush-queue can be used for this domain to flu=
sh iotlb. Could the code change in this patch bring any performance impact =
to this case?

Regards,
-Tina