Received-SPF: pass (google.com: domain of linux-kernel+bounces-144570-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223;
From: Xu Yang <xu.yang_2@nxp.com>
To: frank.li@nxp.com,
	will@kernel.org,
	mark.rutland@arm.com,
	robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org,
	shawnguo@kernel.org,
	s.hauer@pengutronix.de,
	kernel@pengutronix.de,
	festevam@gmail.com,
	john.g.garry@oracle.com,
	jolsa@kernel.org,
	namhyung@kernel.org,
	irogers@google.com
Cc: mike.leach@linaro.org,
	peterz@infradead.org,
	mingo@redhat.com,
	acme@kernel.org,
	alexander.shishkin@linux.intel.com,
	adrian.hunter@intel.com,
	linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-perf-users@vger.kernel.org,
	imx@lists.linux.dev
Subject: [PATCH v10 5/8] perf: imx_perf: fix counter start and config sequence
Date: Mon, 15 Apr 2024 14:13:17 +0800
Message-Id: <20240415061320.3948707-5-xu.yang_2@nxp.com>
In-Reply-To: <20240415061320.3948707-1-xu.yang_2@nxp.com>
References: <20240415061320.3948707-1-xu.yang_2@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?+PIOVpIH8BPpl82MPlHR23qY26nglsO3/xz28XvBJcLrDVrI4xuINw7vEmX2?=
 =?us-ascii?Q?Jyu6qWgq3LeL1f1aNV1rHxz9Av4/MK9xZC3A+2ToiaoJgY5xFkyCaySDFQ2r?=
 =?us-ascii?Q?r0vF4SmrGV3drkGAY0OpBQmV+pGJRIS+nWU1uinHPmNTJG30gO0+m+KD1JWn?=
 =?us-ascii?Q?OhH1VxjIRG6BNkanPAPwJPosanN8wWr5v22oPXesLoA8ABGDmkWWeV74vpLQ?=
 =?us-ascii?Q?ctUwnKLzwLiXHkhhpxZOmsfxEf10qZ/OcugSjLod+eV4UknzGgwNYMSXEzT4?=
 =?us-ascii?Q?rEcJ/el9xwTzY0VCpoHpwJdV5qLbJ7POFhD1KDgBzPsgwuImLTjttFn7cnt4?=
 =?us-ascii?Q?7ctwqDD8AZvY+iU9v/oBCYIc0HWOwcjHYy/iVmLsGjDOHO/yfVMyWwYFJKI7?=
 =?us-ascii?Q?KzcHjJg3PYGjBMIRVzD5wWxbzrcpuxEtTBeNj4OpSOZ7wXcq3fQiPIFC+14E?=
 =?us-ascii?Q?dCyeeyVl1YY4kym9D2GzZyvY0OIrcuvA/pxdJWUruin95d/eMfY8qT8HiBPm?=
 =?us-ascii?Q?r1Nu+e0SZBlAm6JB/2Kd1oOvatreTtiX42dCmWESUjC7EQoOuwkQGcbhsFTI?=
 =?us-ascii?Q?/Vs2OQy5E/fr2pwwpWUoK6/u04fDhylUmWfime0c/AxmTySmq0bnVRXwoPYQ?=
 =?us-ascii?Q?0obVbOP4fbwuYEC2MD405uPyZZG44ncRWWsa/Z0kVySwIHBXCnscmT97M53N?=
 =?us-ascii?Q?Xpgu69btzu/cEhyDARTTj5e4bDXmRQ/Bz3Kwt8/T1h/fch+/5KpReIdTBJ/f?=
 =?us-ascii?Q?O4olPiFv3dl7SrzOCPtBFPIRU9bYEILHnglwvYOPkLH3oWri57k/3CA1jbYh?=
 =?us-ascii?Q?zYvcpSVuMEHUMWUf6Dd99gTqpYlnGCBAnNONfnm+iwz2gUMU61Pv+aNf/Cee?=
 =?us-ascii?Q?mM5nRc6MFOr/FG3/NKYVQy+PtyXTR7Vp8xW6dJZgH7cIjz/520UwshQe6OH9?=
 =?us-ascii?Q?EVNEdQAUlZKOoKMmSg7xudYa+MkyRdV3+39VizqdS93aXtgpNzp1LTVV01Oy?=
 =?us-ascii?Q?U2B9qpChKZyLjo+6O0kaEI2HTknmn8BzA2nj6e+g8gcFglavSVfIvuY6QneX?=
 =?us-ascii?Q?bHY8HTjHj8bTYC5BY25DqvtxVC/hxPxeil/ifa8pi1rLYWf8jduuHFGZcCOU?=
 =?us-ascii?Q?pF54JayOXyyoXG/AHFnZ/bWfNj6vD2i3uzClUFveXhPVTiVF4tSO1aqmcrMy?=
 =?us-ascii?Q?bKsB1VzRJlseTAjF4bZ0ux56vTUJrgJUJ86ay5f5iBEcZryWatg5N7v/2V5J?=
 =?us-ascii?Q?xFSdXg+VEh0Z283zvQEAHWja29OUx7EjtUZIBZ7ZAMMI0MuVE5+l7RlfVn8X?=
 =?us-ascii?Q?+j+EVeGmexUyqQEc6iO6ZM00tBOLqx1BTnSddUKNZc+KNCMXWzKxZKjsaUn8?=
 =?us-ascii?Q?ZEKgtrqtr0Taq6yeoSHuXsbnMiOvesleg3DE0t6jkV5R3LiGv4qYcHu+IY8p?=
 =?us-ascii?Q?gopjzL9HNkiXuCOzLeashjby7AekLPf/RpPg//8Ovc27V2EPfpyX8NS35/vM?=
 =?us-ascii?Q?vvKvftWnULfIfJvn6WNaa1sRWa7JD+AzKOCT2xY4UIzvGIGDtEObPjeuXddg?=
 =?us-ascii?Q?drCeSe/9X5lpTZsPwJ9dxJw5bMJZN+M8lX/EP++G?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: b0bc4ca4-5bc6-41f9-7ce2-08dc5d1321fd
X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8822.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2024 06:13:14.1051
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: Pzxq7IRI/wiFEqFqn9RMj1JIt7LFFbozl+jc5d1j5BZoDFXbwPlsWLRf2tk/zrUNJ8eKSpEzxMb6VJOrTsgeSw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1PR04MB10117

In current driver, the counter will start firstly and then be configured.
This sequence is not correct for AXI filter events since the correct
AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Fixes: 55691f99d417 ("drivers/perf: imx_ddr: Add support for NXP i.MX9 SoC DDRC PMU driver")
cc: <stable@vger.kernel.org>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

---
Changes in v5:
 - new patch
Changes in v6:
 - no changes
Changes in v7:
 - no changes
Changes in v8:
 - add fix tag
Changes in v9:
 - add Rb tag
Changes in v10:
 - no changes
---
 drivers/perf/fsl_imx9_ddr_perf.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index dffe7c1e4809..53cb2842956d 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -541,12 +541,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
 	hwc->idx = counter;
 	hwc->state |= PERF_HES_STOPPED;
 
-	if (flags & PERF_EF_START)
-		ddr_perf_event_start(event, flags);
-
 	/* read trans, write trans, read beat */
 	imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
 
+	if (flags & PERF_EF_START)
+		ddr_perf_event_start(event, flags);
+
 	return 0;
 }
 
-- 
2.34.1