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Message-ID: <a5c4b57b-c1f8-4f75-95e4-9a462f4673c9@linux.intel.com>
Date: Mon, 15 Apr 2024 13:00:20 +0800
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Cc: baolu.lu@linux.intel.com, "Tian, Kevin" <kevin.tian@intel.com>,
 Jacob Pan <jacob.jun.pan@linux.intel.com>, Joerg Roedel <joro@8bytes.org>,
 Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>,
 "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 1/1] iommu/vt-d: Remove caching mode check before
 device TLB flush
To: Yi Liu <yi.l.liu@intel.com>, "Zhang, Tina" <tina.zhang@intel.com>,
 "iommu@lists.linux.dev" <iommu@lists.linux.dev>
References: <20240415013835.9527-1-baolu.lu@linux.intel.com>
 <MW5PR11MB58818970CB8E9A37A6AF563889092@MW5PR11MB5881.namprd11.prod.outlook.com>
 <f3502244-5f37-4f44-94a5-39939ba20eec@intel.com>
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From: Baolu Lu <baolu.lu@linux.intel.com>
In-Reply-To: <f3502244-5f37-4f44-94a5-39939ba20eec@intel.com>
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On 4/15/24 10:43 AM, Yi Liu wrote:
> On 2024/4/15 10:22, Zhang, Tina wrote:
>>
>>
>>> -----Original Message-----
>>> From: Lu Baolu <baolu.lu@linux.intel.com>
>>> Sent: Monday, April 15, 2024 9:39 AM
>>> To: iommu@lists.linux.dev
>>> Cc: Tian, Kevin <kevin.tian@intel.com>; Liu, Yi L 
>>> <yi.l.liu@intel.com>; Jacob
>>> Pan <jacob.jun.pan@linux.intel.com>; Joerg Roedel <joro@8bytes.org>; 
>>> Will
>>> Deacon <will@kernel.org>; Robin Murphy <robin.murphy@arm.com>; linux-
>>> kernel@vger.kernel.org; Lu Baolu <baolu.lu@linux.intel.com>
>>> Subject: [PATCH v3 1/1] iommu/vt-d: Remove caching mode check before
>>> device TLB flush
>>>
>>> The Caching Mode (CM) of the Intel IOMMU indicates if the hardware
>>> implementation caches not-present or erroneous translation-structure 
>>> entries
>>> except for the first-stage translation. The caching mode is 
>>> irrelevant to the
>>> device TLB, therefore there is no need to check it before a device TLB
>>> invalidation operation.
>>>
>>> Remove two caching mode checks before device TLB invalidation in the 
>>> driver.
>>> The removal of these checks doesn't change the driver's behavior in 
>>> critical
>>> map/unmap paths. Hence, there is no functionality or performance impact,
>>> especially since commit <29b32839725f> ("iommu/vt-d:
>>> Do not use flush-queue when caching-mode is on") has already disabled
>>> flush-queue for caching mode. Therefore, caching mode will never call
>>> intel_flush_iotlb_all().
>> The current logic is if the caching mode is being used and a domain 
>> isn't using first level I/O page table, then flush-queue won't be 
>> used. Otherwise, the flush-queue can be enabled.
>> See https://github.com/torvalds/linux/commit/257ec29074
>>
>> In other words, if the caching mode is being used and a domain is 
>> using first level I/O page table, the flush-queue can be used for this 
>> domain to flush iotlb. Could the code change in this patch bring any 
>> performance impact to this case?
> 
> This seems to have performance deduction in the nested translation case.
> The iommufd nested support bas been merged in 6.8, while the Qemu side
> is wip. So this performance deduction does not happen until Qemu is
> done. Should this also be considered as a performance regression? TBH.

Caching mode is irrelevant to first-stage and nesting translations. If
the QEMU implementation still relies on caching mode for nesting
support, it's already broken.

Best regards,
baolu