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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id fd23-20020a056402389700b0057021b811eesm1735813edb.67.2024.04.15.06.36.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 06:36:03 -0700 (PDT) Date: Mon, 15 Apr 2024 15:36:02 +0200 From: Andrew Jones To: Atish Patra Cc: linux-kernel@vger.kernel.org, Anup Patel , Ajay Kaher , Albert Ou , Alexandre Ghiti , Alexey Makhalov , Atish Patra , Broadcom internal kernel review list , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, Will Deacon , x86@kernel.org Subject: Re: [PATCH v6 23/24] KVM: riscv: selftests: Add a test for counter overflow Message-ID: <20240415-418eb2e18cfeb613d252fff0@orel> References: <20240411000752.955910-1-atishp@rivosinc.com> <20240411000752.955910-24-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240411000752.955910-24-atishp@rivosinc.com> On Wed, Apr 10, 2024 at 05:07:51PM -0700, Atish Patra wrote: > Add a test for verifying overflow interrupt. Currently, it relies on > overflow support on cycle/instret events. This test works for cycle/ > instret events which support sampling via hpmcounters on the platform. > There are no ISA extensions to detect if a platform supports that. Thus, > this test will fail on platform with virtualization but doesn't > support overflow on these two events. > > Reviewed-by: Anup Patel > Signed-off-by: Atish Patra > --- > .../selftests/kvm/riscv/sbi_pmu_test.c | 113 ++++++++++++++++++ > 1 file changed, 113 insertions(+) > Reviewed-by: Andrew Jones