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AJvYcCVXSXH+Bj3oU6SlOzxQPMQJhFDQmt/+nzDBaiv6TByQYxqXq6O0DCs51wkodbZbkD9fEUp89S9wPY4alspuE4XlX4HVi2x8TDIdnh9X X-Gm-Message-State: AOJu0Yz2L9irheoe84DXkcSn01RnL0npSI2B6hOGM5Cm6bGo8AmTc4XX grtxxzWPZz06mxXFghB3e3gUrX8QXCRpJ+J9lAoQ0tCwnNc2n0w1dmAu+D71Gcw= X-Received: by 2002:a05:6a21:3381:b0:1a7:58ca:cdf3 with SMTP id yy1-20020a056a21338100b001a758cacdf3mr14872194pzb.8.1713200503358; Mon, 15 Apr 2024 10:01:43 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.230]) by smtp.gmail.com with ESMTPSA id 1-20020a056a00072100b006ed045e3a70sm7433158pfm.25.2024.04.15.10.01.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 10:01:42 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Haibo1 Xu , Conor Dooley , Andrew Jones , Atish Kumar Patra , Andrei Warkentin , Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [RFC PATCH v4 03/20] PCI: Make pci_create_root_bus() declare its reliance on MSI domains Date: Mon, 15 Apr 2024 22:30:56 +0530 Message-Id: <20240415170113.662318-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240415170113.662318-1-sunilvl@ventanamicro.com> References: <20240415170113.662318-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Similar to commit 9ec37efb8783 ("PCI/MSI: Make pci_host_common_probe() declare its reliance on MSI domains"), declare this dependency for PCI probe in ACPI based flow. This is required especially for RISC-V platforms where MSI controller can be absent. However, setting this for all architectures seem to cause issues on non RISC-V architectures [1]. Hence, enabled this only for RISC-V. [1] - https://lore.kernel.org/oe-lkp/202403041047.791cb18e-oliver.sang@intel.com Signed-off-by: Sunil V L --- drivers/pci/probe.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 1325fbae2f28..e09915bee2ee 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -3048,6 +3048,9 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus, bridge->sysdata = sysdata; bridge->busnr = bus; bridge->ops = ops; +#ifdef CONFIG_RISCV + bridge->msi_domain = true; +#endif error = pci_register_host_bridge(bridge); if (error < 0) -- 2.40.1