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[98.197.58.203]) by smtp.gmail.com with ESMTPSA id e20-20020a05680809b400b003c5e679337esm1729084oig.47.2024.04.15.13.07.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Apr 2024 13:07:04 -0700 (PDT) Message-ID: <3cfc26e6-5587-d4a2-f217-1a30169ad1a0@gmail.com> Date: Mon, 15 Apr 2024 15:07:02 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v3 4/7] PCI: qcom: Add support for IPQ9574 Content-Language: en-US To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Michael Turquette , Stephen Boyd , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org References: <20240415182052.374494-1-mr.nuke.me@gmail.com> <20240415182052.374494-5-mr.nuke.me@gmail.com> From: mr.nuke.me@gmail.com In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 4/15/24 15:04, Dmitry Baryshkov wrote: > On Mon, 15 Apr 2024 at 21:22, Alexandru Gagniuc wrote: >> >> Add support for the PCIe on IPQ9574. The main difference from ipq6018 >> is that the "iface" clock is not necessarry. Add a special case in >> qcom_pcie_get_resources_2_9_0() to handle this. >> >> Signed-off-by: Alexandru Gagniuc >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++---- >> 1 file changed, 9 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 14772edcf0d3..10560d6d6336 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -1101,15 +1101,19 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) >> struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; >> struct dw_pcie *pci = pcie->pci; >> struct device *dev = pci->dev; >> - int ret; >> + int ret, num_clks = ARRAY_SIZE(res->clks) - 1; >> >> - res->clks[0].id = "iface"; >> + res->clks[0].id = "rchng"; >> res->clks[1].id = "axi_m"; >> res->clks[2].id = "axi_s"; >> res->clks[3].id = "axi_bridge"; >> - res->clks[4].id = "rchng"; >> >> - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); >> + if (!of_device_is_compatible(dev->of_node, "qcom,pcie-ipq9574")) { >> + res->clks[4].id = "iface"; >> + num_clks++; >> + } >> + >> + ret = devm_clk_bulk_get(dev, num_clks, res->clks); > > Just use devm_clk_bulk_get_optional() here. Thank you! I wasn't sure if this was the correct solution here. I will get this updated in v4. Alex >> if (ret < 0) >> return ret; >> >> @@ -1664,6 +1668,7 @@ static const struct of_device_id qcom_pcie_match[] = { >> { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, >> { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, >> { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, >> + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 }, >> { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, >> { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, >> { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp }, >> -- >> 2.40.1 >> >> > >