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Tue, 16 Apr 2024 09:15:55 +0100 Date: Tue, 16 Apr 2024 09:15:54 +0100 Message-ID: <864jc1soxx.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Jonathan Corbet , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [RFC 5/8] KVM: arm64: Explicitly handle MDSELR_EL1 traps as UNDEFINED In-Reply-To: <58cdb927-a2d9-4af4-900f-2132472afe9f@arm.com> References: <20240405080008.1225223-1-anshuman.khandual@arm.com> <20240405080008.1225223-6-anshuman.khandual@arm.com> <86a5m8t8s6.wl-maz@kernel.org> <5a2a74b3-f6cd-4cb6-8ee8-5dd7dc2bd686@arm.com> <86mspysuw8.wl-maz@kernel.org> <58cdb927-a2d9-4af4-900f-2132472afe9f@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, corbet@lwn.net, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, mark.rutland@arm.com, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 16 Apr 2024 06:46:13 +0100, Anshuman Khandual wrote: > > On 4/12/24 16:35, Marc Zyngier wrote: > > kvm_init_nv_sysregs() to ensure that these new registers have the > > correct RES0/RES1 behaviour depending on the supported feature set for > > the guest. > > Following might be sufficient for MDSELR_EL1, but wondering if these fine > grained control registers (HDFG[RW]TR2_EL2) need to be completely defined > for the entire guest feature set, probably required. Yes, you should check for all features defining a valid bit in these registers, and apply the correct mask if the feature isn't advertised to the guest, even if KVM doesn't currently support the feature at all. This is a bit cumbersome at first, but we don't have to revisit it when the feature gets enabled, which is a massive maintainability improvement. It also means that we just have to read the documentation and match it against the code, which should be pretty trivial. > > /* HDFG[RW]TR2_EL2 */ > res0 = res1 = 0; > if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DebugVer, V8P9)) > res0 |= HDFGRTR2_EL2_nMDSELR_EL1; > set_sysreg_masks(kvm, HDFGRTR2_EL2, res0 | HDFGRTR2_EL2_RES0, res1); > set_sysreg_masks(kvm, HDFGWTR2_EL2, res0 | HDFGWTR2_EL2_RES0, res1); Yup, this looks sensible for that particular bit. A few more to go... ;-) Thanks, M. -- Without deviation from the norm, progress is not possible.