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[2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id q29-20020a05620a025d00b0078ecf9c3480si9058367qkn.555.2024.04.16.02.35.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Apr 2024 02:35:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-146558-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of linux-kernel+bounces-146558-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-146558-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 86E361C21527 for ; Tue, 16 Apr 2024 09:35:42 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EBA2885C69; Tue, 16 Apr 2024 09:35:30 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D28B184E0A; Tue, 16 Apr 2024 09:35:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713260130; cv=none; b=MGijnzhyLtbzMY6nRJyAb9cy2XM1Zirej+DRYIICQFZ2D2p5+3YWir6lGqBPprvIRCl52L+RY+HM4aIbWPVabkkZvOBi5UUAdlW0NLxgG3F+s8mLvFr/Vz68LZvdzs97xhHSIkHmfw0Iwhp7WUeRm3MGOg6AJzvPfB81ShFS45g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713260130; c=relaxed/simple; bh=TNm9wA9VCf4GRpizHagVxFmlH0uk3TxbxAtSjpVSKiY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=nGlQ5+0CmJTlqMXrtZhxJ/o5LY02aPo+EeTrJHK67e5kkrZJTtBcnA8+5NWlyFgvXPi0SG/h76D06cX874rPYVQ61AG+EXB0ZOEvjEqRf77OvA+cP1BkKvNeKRRWtqQCzzd+MjUcsjeUTR0qKeqaGAnJvu82IBqEzTZwURzuN5w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 28C53339; Tue, 16 Apr 2024 02:35:56 -0700 (PDT) Received: from bogus (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5B0A83F792; Tue, 16 Apr 2024 02:35:25 -0700 (PDT) Date: Tue, 16 Apr 2024 10:35:22 +0100 From: Sudeep Holla To: Elliot Berman Cc: Bjorn Andersson , Konrad Dybcio , Sudeep Holla , Sebastian Reichel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , , Subject: Re: [PATCH v2 0/4] Implement vendor resets for PSCI SYSTEM_RESET2 Message-ID: References: <20240414-arm-psci-system_reset2-vendor-reboots-v2-0-da9a055a648f@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240414-arm-psci-system_reset2-vendor-reboots-v2-0-da9a055a648f@quicinc.com> On Sun, Apr 14, 2024 at 12:30:23PM -0700, Elliot Berman wrote: > The PSCI SYSTEM_RESET2 call allows vendor firmware to define additional > reset types which could be mapped to the reboot argument. > > Setting up reboot on Qualcomm devices can be inconsistent from chipset > to chipset. That doesn't sound good. Do you mean PSCI SYSTEM_RESET doesn't work as expected ? Does it mean it is not conformant to the specification ? > Generally, there is a PMIC register that gets written to > decide the reboot type. There is also sometimes a cookie that can be > written to indicate that the bootloader should behave differently than a > regular boot. These knobs evolve over product generations and require > more drivers. Qualcomm firmwares are beginning to expose vendor > SYSTEM_RESET2 types to simplify driver requirements from Linux. > Why can't this be fully userspace driven ? What is the need to keep the cookie in the DT ? -- Regards, Sudeep