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For example, in the TX base spec, section 15.2 "On-TD Performance Monitoring", subsection "15.2.1 Overview": * IA32_DS_AREA MSR is context-switched across TD entry and exit transitions. To confirm I peeked at the TDX module code and found (if I understand this correctly) that IA32_DS_AREA is saved on TD entry (see [1]) and restored on TD exit (see [2]). > Signed-off-by: Isaku Yamahata > Reviewed-by: Paolo Bonzini > --- > arch/x86/events/intel/ds.c | 1 + > arch/x86/kvm/vmx/tdx.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c > index d49d661ec0a7..25670d8a485b 100644 > --- a/arch/x86/events/intel/ds.c > +++ b/arch/x86/events/intel/ds.c > @@ -2428,3 +2428,4 @@ void perf_restore_debug_store(void) > > wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); > } > +EXPORT_SYMBOL_GPL(perf_restore_debug_store); > diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c > index b8b168f74dfe..ad4d3d4eaf6c 100644 > --- a/arch/x86/kvm/vmx/tdx.c > +++ b/arch/x86/kvm/vmx/tdx.c > @@ -665,6 +665,7 @@ fastpath_t tdx_vcpu_run(struct kvm_vcpu *vcpu) > tdx_vcpu_enter_exit(tdx); > > tdx_user_return_update_cache(vcpu); > + perf_restore_debug_store(); > tdx_restore_host_xsave_state(vcpu); > tdx->host_state_need_restore = true; > Reinette [1] https://github.com/intel/tdx-module/blob/tdx_1.5/src/td_transitions/tdh_vp_enter.c#L719 [2] https://github.com/intel/tdx-module/blob/tdx_1.5/src/td_transitions/td_exit.c#L130