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Date: Tue, 16 Apr 2024 15:15:46 -0700
From: Jacob Pan <jacob.jun.pan@linux.intel.com>
To: "Tian, Kevin" <kevin.tian@intel.com>
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Subject: Re: [PATCH v2 12/13] iommu/vt-d: Add an irq_chip for posted MSIs
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Hi Kevin,

On Fri, 12 Apr 2024 09:36:10 +0000, "Tian, Kevin" <kevin.tian@intel.com>
wrote:

> > From: Jacob Pan <jacob.jun.pan@linux.intel.com>
> > Sent: Saturday, April 6, 2024 6:31 AM
> >=20
> > + *
> > + * For the example below, 3 MSIs are coalesced into one CPU
> > notification. Only
> > + * one apic_eoi() is needed.
> > + *
> > + * __sysvec_posted_msi_notification()
> > + *	irq_enter();
> > + *		handle_edge_irq()
> > + *			irq_chip_ack_parent()
> > + *				dummy(); // No EOI
> > + *			handle_irq_event()
> > + *				driver_handler()
> > + *	irq_enter();
> > + *		handle_edge_irq()
> > + *			irq_chip_ack_parent()
> > + *				dummy(); // No EOI
> > + *			handle_irq_event()
> > + *				driver_handler()
> > + *	irq_enter();
> > + *		handle_edge_irq()
> > + *			irq_chip_ack_parent()
> > + *				dummy(); // No EOI
> > + *			handle_irq_event()
> > + *				driver_handler() =20
>=20
> typo: you added three irq_enter()'s here
right, will remove the middle two.

>=20
> > + *	apic_eoi()
> > + * irq_exit()
> > + */
> > +static struct irq_chip intel_ir_chip_post_msi =3D {
> > +	.name			=3D "INTEL-IR-POST",
> > +	.irq_ack		=3D dummy,
> > +	.irq_set_affinity	=3D intel_ir_set_affinity,
> > +	.irq_compose_msi_msg	=3D intel_ir_compose_msi_msg,
> > +	.irq_set_vcpu_affinity	=3D intel_ir_set_vcpu_affinity,
> > +}; =20
>=20
> What about putting this patch at end of the series (combining the
> change in intel_irq_remapping_alloc()) to finally enable this
> feature?
>=20
> It reads slightly better to me to first get those callbacks extended
> to deal with the new mechanism (i.e. most changes in patch13)
> before using them in the new irqchip. =F0=9F=98=8A

makes sense, will do.

Thanks,

Jacob