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Date: Wed, 17 Apr 2024 02:29:37 -0400
From: Guo Ren <guoren@kernel.org>
To: Yangyu Chen <cyy@cyyself.name>
Cc: dqfext@gmail.com, ajones@ventanamicro.com, anup@brainfault.org,
	aou@eecs.berkeley.edu, atishp@atishpatra.org,
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	linux-riscv@lists.infradead.org, mark.rutland@arm.com,
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Subject: Re: [PATCH] perf: RISC-V: fix IRQ detection on T-Head C908
Message-ID: <Zh9sUUUT09LZb0MO@gmail.com>
References: <20240311063018.1886757-1-dqfext@gmail.com>
 <tencent_29B81A312921AB8D9D7C3C8292DAAB8EF608@qq.com>
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On Fri, Apr 12, 2024 at 02:09:32PM +0800, Yangyu Chen wrote:
> On 2024/3/11 14:30, Qingfang Deng wrote:
> > T-Head C908 has the same IRQ num and CSR as previous C9xx cores, but
> > reports non-zero marchid and mimpid. Remove the ID checks.
> > 
> > Fixes: 65e9fb081877 ("drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores")
> > Signed-off-by: Qingfang Deng<dqfext@gmail.com>
> > ---
> >   arch/riscv/errata/thead/errata.c | 4 ----
> >   drivers/perf/riscv_pmu_sbi.c     | 4 +---
> >   2 files changed, 1 insertion(+), 7 deletions(-)
> > 
> > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > index b1c410bbc1ae..49ccad5b21bb 100644
> > --- a/arch/riscv/errata/thead/errata.c
> > +++ b/arch/riscv/errata/thead/errata.c
> > @@ -125,10 +125,6 @@ static bool errata_probe_pmu(unsigned int stage,
> >   	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
> >   		return false;
> >   
> > -	/* target-c9xx cores report arch_id and impid as 0 */
> > -	if (arch_id != 0 || impid != 0)
> > -		return false;
> > -
> >   	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> >   		return false;
> >   
> > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > index 452aab49db1e..87b83184383a 100644
> > --- a/drivers/perf/riscv_pmu_sbi.c
> > +++ b/drivers/perf/riscv_pmu_sbi.c
> > @@ -811,9 +811,7 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
> >   		riscv_pmu_irq_num = RV_IRQ_PMU;
> >   		riscv_pmu_use_irq = true;
> >   	} else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
> > -		   riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
> > -		   riscv_cached_marchid(0) == 0 &&
> > -		   riscv_cached_mimpid(0) == 0) {
> > +		   riscv_cached_mvendorid(0) == THEAD_VENDOR_ID) {
> >   		riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
> >   		riscv_pmu_use_irq = true;
> >   	}
> > -- 2.34.1
> 
> Tested-by: Yangyu Chen <cyy@cyyself.name>
> 
> With this patch and T-Head C908 PMU being probed by OpenSBI, I can now use
> the perf record to profile RVV 1.0 software on Canaan Kendryte K230. This
> will speed up many RVV 1.0 software developments now and even for better
> performance.
> 
> However, as Inochi said, the newer version, C908 may support Sccofpmf. We
> should ask Guo Ren to clarify this so we can have the cleanest way to
> probe what to use between THEAD_PMU and Sscofpmu.
> 
> I added CC to Guo Ren. Please clarify about this.

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index c6ef09c4548c..ee6fa5b65b53 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -812,8 +812,10 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu
*pmu, struct platform_device *pde
                riscv_pmu_use_irq = true;
        } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
                   riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
-                  riscv_cached_marchid(0) == 0 &&
-                  riscv_cached_mimpid(0) == 0) {
+                  (riscv_cached_marchid(0) == 0 ||
+                   riscv_cached_marchid(0) == 0x8000000009140d00) &&
+                  (riscv_cached_mimpid(0) == 0 ||
+                   riscv_cached_mimpid(0) == 0x50000)) {
                riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
                riscv_pmu_use_irq = true;
        }

Only k230's c908 has the problem, not all XuanTie Processors. We just
need to pick it out. Could the above satisfy you?

> 
> Some off-topic things:
> 
> I need this feature recently since I am implementing a pure RVV chacha20
> algorithm. I have already sent PR to openssl to speed up the crypto
> performance on RVV without Zvkb support and maybe ported to kernel crypto
> sometimes. To speed up TLS or other applications for many chips that may
> come this year with RVV 1.0 but without Zvkb.
> 
> Link: https://github.com/openssl/openssl/pull/24069
> 
> However, the performance evaluation on K230 is not well compared to pure C
> implementation. I will need this PMU driver to do some profiling.
> 
> Thanks,
> Yangyu Chen
> 
> 
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