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References: <20240416211941.9369-1-tony.luck@intel.com> <20240416212304.10028-1-tony.luck@intel.com>
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From: "Rafael J. Wysocki" <rafael@kernel.org>
Date: Wed, 17 Apr 2024 10:24:49 +0200
Message-ID: <CAJZ5v0hZe6hC6vLoQHk7iqaf3TSu9GRkG9M879P5Vuy90Pzybg@mail.gmail.com>
Subject: Re: [PATCH v3 72/74] x86/cpu/vfm: Update tools/power/x86/turbostat/turbostat.c
To: Tony Luck <tony.luck@intel.com>
Cc: linux-kernel@vger.kernel.org, Len Brown <lenb@kernel.org>, linux-pm@vger.kernel.org, 
	patches@lists.linux.dev
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On Tue, Apr 16, 2024 at 11:35=E2=80=AFPM Tony Luck <tony.luck@intel.com> wr=
ote:
>
> New CPU #defines encode vendor and family as well as model.
>
> Signed-off-by: Tony Luck <tony.luck@intel.com>

Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

> ---
>  tools/power/x86/turbostat/turbostat.c | 161 +++++++++++++++-----------
>  1 file changed, 93 insertions(+), 68 deletions(-)
>
> diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turb=
ostat/turbostat.c
> index 98256468e248..80dc3bdaa5fc 100644
> --- a/tools/power/x86/turbostat/turbostat.c
> +++ b/tools/power/x86/turbostat/turbostat.c
> @@ -9,6 +9,30 @@
>
>  #define _GNU_SOURCE
>  #include MSRHEADER
> +
> +// copied from arch/x86/include/asm/cpu_device_id.h
> +#define VFM_MODEL_BIT  0
> +#define VFM_FAMILY_BIT 8
> +#define VFM_VENDOR_BIT 16
> +#define VFM_RSVD_BIT   24
> +
> +#define        VFM_MODEL_MASK  GENMASK(VFM_FAMILY_BIT - 1, VFM_MODEL_BIT=
)
> +#define        VFM_FAMILY_MASK GENMASK(VFM_VENDOR_BIT - 1, VFM_FAMILY_BI=
T)
> +#define        VFM_VENDOR_MASK GENMASK(VFM_RSVD_BIT - 1, VFM_VENDOR_BIT)
> +
> +#define VFM_MODEL(vfm) (((vfm) & VFM_MODEL_MASK) >> VFM_MODEL_BIT)
> +#define VFM_FAMILY(vfm)        (((vfm) & VFM_FAMILY_MASK) >> VFM_FAMILY_=
BIT)
> +#define VFM_VENDOR(vfm)        (((vfm) & VFM_VENDOR_MASK) >> VFM_VENDOR_=
BIT)
> +
> +#define        VFM_MAKE(_vendor, _family, _model) (    \
> +       ((_model) << VFM_MODEL_BIT) |           \
> +       ((_family) << VFM_FAMILY_BIT) |         \
> +       ((_vendor) << VFM_VENDOR_BIT)           \
> +)
> +// end copied section
> +
> +#define X86_VENDOR_INTEL       0
> +
>  #include INTEL_FAMILY_HEADER
>  #include <stdarg.h>
>  #include <stdio.h>
> @@ -334,7 +358,7 @@ struct platform_features {
>  };
>
>  struct platform_data {
> -       unsigned int model;
> +       unsigned int vfm;
>         const struct platform_features *features;
>  };
>
> @@ -860,73 +884,73 @@ static const struct platform_features amd_features_=
with_rapl =3D {
>  };
>
>  static const struct platform_data turbostat_pdata[] =3D {
> -       { INTEL_FAM6_NEHALEM, &nhm_features },
> -       { INTEL_FAM6_NEHALEM_G, &nhm_features },
> -       { INTEL_FAM6_NEHALEM_EP, &nhm_features },
> -       { INTEL_FAM6_NEHALEM_EX, &nhx_features },
> -       { INTEL_FAM6_WESTMERE, &nhm_features },
> -       { INTEL_FAM6_WESTMERE_EP, &nhm_features },
> -       { INTEL_FAM6_WESTMERE_EX, &nhx_features },
> -       { INTEL_FAM6_SANDYBRIDGE, &snb_features },
> -       { INTEL_FAM6_SANDYBRIDGE_X, &snx_features },
> -       { INTEL_FAM6_IVYBRIDGE, &ivb_features },
> -       { INTEL_FAM6_IVYBRIDGE_X, &ivx_features },
> -       { INTEL_FAM6_HASWELL, &hsw_features },
> -       { INTEL_FAM6_HASWELL_X, &hsx_features },
> -       { INTEL_FAM6_HASWELL_L, &hswl_features },
> -       { INTEL_FAM6_HASWELL_G, &hswg_features },
> -       { INTEL_FAM6_BROADWELL, &bdw_features },
> -       { INTEL_FAM6_BROADWELL_G, &bdwg_features },
> -       { INTEL_FAM6_BROADWELL_X, &bdx_features },
> -       { INTEL_FAM6_BROADWELL_D, &bdx_features },
> -       { INTEL_FAM6_SKYLAKE_L, &skl_features },
> -       { INTEL_FAM6_SKYLAKE, &skl_features },
> -       { INTEL_FAM6_SKYLAKE_X, &skx_features },
> -       { INTEL_FAM6_KABYLAKE_L, &skl_features },
> -       { INTEL_FAM6_KABYLAKE, &skl_features },
> -       { INTEL_FAM6_COMETLAKE, &skl_features },
> -       { INTEL_FAM6_COMETLAKE_L, &skl_features },
> -       { INTEL_FAM6_CANNONLAKE_L, &cnl_features },
> -       { INTEL_FAM6_ICELAKE_X, &icx_features },
> -       { INTEL_FAM6_ICELAKE_D, &icx_features },
> -       { INTEL_FAM6_ICELAKE_L, &cnl_features },
> -       { INTEL_FAM6_ICELAKE_NNPI, &cnl_features },
> -       { INTEL_FAM6_ROCKETLAKE, &cnl_features },
> -       { INTEL_FAM6_TIGERLAKE_L, &cnl_features },
> -       { INTEL_FAM6_TIGERLAKE, &cnl_features },
> -       { INTEL_FAM6_SAPPHIRERAPIDS_X, &spr_features },
> -       { INTEL_FAM6_EMERALDRAPIDS_X, &spr_features },
> -       { INTEL_FAM6_GRANITERAPIDS_X, &spr_features },
> -       { INTEL_FAM6_LAKEFIELD, &cnl_features },
> -       { INTEL_FAM6_ALDERLAKE, &adl_features },
> -       { INTEL_FAM6_ALDERLAKE_L, &adl_features },
> -       { INTEL_FAM6_RAPTORLAKE, &adl_features },
> -       { INTEL_FAM6_RAPTORLAKE_P, &adl_features },
> -       { INTEL_FAM6_RAPTORLAKE_S, &adl_features },
> -       { INTEL_FAM6_METEORLAKE, &cnl_features },
> -       { INTEL_FAM6_METEORLAKE_L, &cnl_features },
> -       { INTEL_FAM6_ARROWLAKE, &cnl_features },
> -       { INTEL_FAM6_LUNARLAKE_M, &cnl_features },
> -       { INTEL_FAM6_ATOM_SILVERMONT, &slv_features },
> -       { INTEL_FAM6_ATOM_SILVERMONT_D, &slvd_features },
> -       { INTEL_FAM6_ATOM_AIRMONT, &amt_features },
> -       { INTEL_FAM6_ATOM_GOLDMONT, &gmt_features },
> -       { INTEL_FAM6_ATOM_GOLDMONT_D, &gmtd_features },
> -       { INTEL_FAM6_ATOM_GOLDMONT_PLUS, &gmtp_features },
> -       { INTEL_FAM6_ATOM_TREMONT_D, &tmtd_features },
> -       { INTEL_FAM6_ATOM_TREMONT, &tmt_features },
> -       { INTEL_FAM6_ATOM_TREMONT_L, &tmt_features },
> -       { INTEL_FAM6_ATOM_GRACEMONT, &adl_features },
> -       { INTEL_FAM6_ATOM_CRESTMONT_X, &srf_features },
> -       { INTEL_FAM6_ATOM_CRESTMONT, &grr_features },
> -       { INTEL_FAM6_XEON_PHI_KNL, &knl_features },
> -       { INTEL_FAM6_XEON_PHI_KNM, &knl_features },
> +       { INTEL_NEHALEM, &nhm_features },
> +       { INTEL_NEHALEM_G, &nhm_features },
> +       { INTEL_NEHALEM_EP, &nhm_features },
> +       { INTEL_NEHALEM_EX, &nhx_features },
> +       { INTEL_WESTMERE, &nhm_features },
> +       { INTEL_WESTMERE_EP, &nhm_features },
> +       { INTEL_WESTMERE_EX, &nhx_features },
> +       { INTEL_SANDYBRIDGE, &snb_features },
> +       { INTEL_SANDYBRIDGE_X, &snx_features },
> +       { INTEL_IVYBRIDGE, &ivb_features },
> +       { INTEL_IVYBRIDGE_X, &ivx_features },
> +       { INTEL_HASWELL, &hsw_features },
> +       { INTEL_HASWELL_X, &hsx_features },
> +       { INTEL_HASWELL_L, &hswl_features },
> +       { INTEL_HASWELL_G, &hswg_features },
> +       { INTEL_BROADWELL, &bdw_features },
> +       { INTEL_BROADWELL_G, &bdwg_features },
> +       { INTEL_BROADWELL_X, &bdx_features },
> +       { INTEL_BROADWELL_D, &bdx_features },
> +       { INTEL_SKYLAKE_L, &skl_features },
> +       { INTEL_SKYLAKE, &skl_features },
> +       { INTEL_SKYLAKE_X, &skx_features },
> +       { INTEL_KABYLAKE_L, &skl_features },
> +       { INTEL_KABYLAKE, &skl_features },
> +       { INTEL_COMETLAKE, &skl_features },
> +       { INTEL_COMETLAKE_L, &skl_features },
> +       { INTEL_CANNONLAKE_L, &cnl_features },
> +       { INTEL_ICELAKE_X, &icx_features },
> +       { INTEL_ICELAKE_D, &icx_features },
> +       { INTEL_ICELAKE_L, &cnl_features },
> +       { INTEL_ICELAKE_NNPI, &cnl_features },
> +       { INTEL_ROCKETLAKE, &cnl_features },
> +       { INTEL_TIGERLAKE_L, &cnl_features },
> +       { INTEL_TIGERLAKE, &cnl_features },
> +       { INTEL_SAPPHIRERAPIDS_X, &spr_features },
> +       { INTEL_EMERALDRAPIDS_X, &spr_features },
> +       { INTEL_GRANITERAPIDS_X, &spr_features },
> +       { INTEL_LAKEFIELD, &cnl_features },
> +       { INTEL_ALDERLAKE, &adl_features },
> +       { INTEL_ALDERLAKE_L, &adl_features },
> +       { INTEL_RAPTORLAKE, &adl_features },
> +       { INTEL_RAPTORLAKE_P, &adl_features },
> +       { INTEL_RAPTORLAKE_S, &adl_features },
> +       { INTEL_METEORLAKE, &cnl_features },
> +       { INTEL_METEORLAKE_L, &cnl_features },
> +       { INTEL_ARROWLAKE, &cnl_features },
> +       { INTEL_LUNARLAKE_M, &cnl_features },
> +       { INTEL_ATOM_SILVERMONT, &slv_features },
> +       { INTEL_ATOM_SILVERMONT_D, &slvd_features },
> +       { INTEL_ATOM_AIRMONT, &amt_features },
> +       { INTEL_ATOM_GOLDMONT, &gmt_features },
> +       { INTEL_ATOM_GOLDMONT_D, &gmtd_features },
> +       { INTEL_ATOM_GOLDMONT_PLUS, &gmtp_features },
> +       { INTEL_ATOM_TREMONT_D, &tmtd_features },
> +       { INTEL_ATOM_TREMONT, &tmt_features },
> +       { INTEL_ATOM_TREMONT_L, &tmt_features },
> +       { INTEL_ATOM_GRACEMONT, &adl_features },
> +       { INTEL_ATOM_CRESTMONT_X, &srf_features },
> +       { INTEL_ATOM_CRESTMONT, &grr_features },
> +       { INTEL_XEON_PHI_KNL, &knl_features },
> +       { INTEL_XEON_PHI_KNM, &knl_features },
>         /*
>          * Missing support for
> -        * INTEL_FAM6_ICELAKE
> -        * INTEL_FAM6_ATOM_SILVERMONT_MID
> -        * INTEL_FAM6_ATOM_AIRMONT_MID
> -        * INTEL_FAM6_ATOM_AIRMONT_NP
> +        * INTEL_ICELAKE
> +        * INTEL_ATOM_SILVERMONT_MID
> +        * INTEL_ATOM_AIRMONT_MID
> +        * INTEL_ATOM_AIRMONT_NP
>          */
>         { 0, NULL },
>  };
> @@ -951,11 +975,12 @@ void probe_platform_features(unsigned int family, u=
nsigned int model)
>                 return;
>         }
>
> -       if (!genuine_intel || family !=3D 6)
> +       if (!genuine_intel)
>                 return;
>
>         for (i =3D 0; turbostat_pdata[i].features; i++) {
> -               if (turbostat_pdata[i].model =3D=3D model) {
> +               if (VFM_FAMILY(turbostat_pdata[i].vfm) =3D=3D family &&
> +                   VFM_MODEL(turbostat_pdata[i].vfm) =3D=3D model) {
>                         platform =3D turbostat_pdata[i].features;
>                         return;
>                 }
> --
> 2.44.0
>
>