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[209.85.128.170]) by smtp.gmail.com with ESMTPSA id l36-20020a81ad24000000b0061248f16528sm133442ywh.66.2024.04.17.08.04.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Apr 2024 08:04:23 -0700 (PDT) Received: by mail-yw1-f170.google.com with SMTP id 00721157ae682-61500da846fso41881367b3.1; Wed, 17 Apr 2024 08:04:23 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCXPiUKAcp1ZvDubQAVdOZetCGyEq+CiX6hGXH6irpndBN1tna5pXjDT5xaDXTKa2vvjE1rSEP8DQRCHMA67vv7uo0m9ZjpDT/v5ZX20R/R38a1oTbJen1TljSIpeLglHadGJv4ZARifqj4xuJL94Bbn25QX4J70dOl2qd6ZNPEgDUHtS1lE/510/DynKSo2pMJvitOFO+zTsyk96eQS+UmD67I39+TpU6Ff X-Received: by 2002:a81:c10c:0:b0:61a:cc3c:ae69 with SMTP id f12-20020a81c10c000000b0061acc3cae69mr9032606ywi.18.1713366263495; Wed, 17 Apr 2024 08:04:23 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240322144355.878930-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240322144355.878930-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20240322144355.878930-6-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 17 Apr 2024 17:04:11 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 5/5] serial: sh-sci: Add support for RZ/V2H(P) SoC To: Prabhakar Cc: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Mar 22, 2024 at 3:45=E2=80=AFPM Prabhakar wrote: > From: Lad Prabhakar > > Add serial support for RZ/V2H(P) SoC with earlycon. > > The SCIF interface in the Renesas RZ/V2H(P) is similar to that available > in the RZ/G2L (R9A07G044) SoC, with the following differences: > > - RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready > and two for Rx and Tx buffer full, all of which are edge-triggered. > - RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both > synchronous and asynchronous modes. > - There are differences in the configuration of certain registers such > as SCSMR, SCFCR, and SCSPTR between the two SoCs. > > To handle these differences on RZ/V2H(P) SoC SCIx_RZV2H_SCIF_REGTYPE > is added. > > Signed-off-by: Lad Prabhakar > --- > Hi Geert, > > To keep the changes minimal I've added a new regtype instead of > port type. > > Cheers, Prabhakar > > v3 - > v4 > - Added SCIx_RZV2H_SCIF_REGTYPE to handle the differences on the > RZ/V2H(P) SoC Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds