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[209.85.219.182]) by smtp.gmail.com with ESMTPSA id ce11-20020a05690c098b00b0061aba26c91esm1733433ywb.97.2024.04.17.07.57.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Apr 2024 07:57:53 -0700 (PDT) Received: by mail-yb1-f182.google.com with SMTP id 3f1490d57ef6-dcc7cdb3a98so5518169276.2; Wed, 17 Apr 2024 07:57:53 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCXqZkZGS7xaKDMNQ6JhK83/pP+YLHa0iBuXqkozvKiXfxd2WMUE8nG6PQ6rZFD+AEHq02EIJicYxaagPdqfrEpEbhAXpD903h8DETgXaKD6SZiKPfq39njBJCOjTw6aBeraM0tr6XU1GbIb6jP5Q7V/OUjVbHB9r52VDeD/BoQiHW7gDGkFOVwLCYqbtnSPIr+TpWzhyzg8U2mOm3rXfBLzF9fjo3CfeS50 X-Received: by 2002:a25:848d:0:b0:dc2:4397:6ad3 with SMTP id v13-20020a25848d000000b00dc243976ad3mr18415156ybk.44.1713365873455; Wed, 17 Apr 2024 07:57:53 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240322144355.878930-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240322144355.878930-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20240322144355.878930-5-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 17 Apr 2024 16:57:41 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 4/5] dt-bindings: serial: Add documentation for Renesas RZ/V2H(P) (R9A09G057) SCIF support To: Prabhakar Cc: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Mar 22, 2024 at 3:45=E2=80=AFPM Prabhakar wrote: > From: Lad Prabhakar > > Document support for the Serial Communication Interface with FIFO (SCIF) > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L > (R9A07G044) SoC, with the following differences: > > - RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready > and two for Rx and Tx buffer full, all of which are edge-triggered. > - RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both > synchronous and asynchronous modes. > - There are differences in the configuration of certain registers such > as SCSMR, SCFCR, and SCSPTR between the two SoCs. > > To handle these differences in the driver, a new SoC-specific compatible > string is added, ensuring proper handling of the unique features and > register configurations of the RZ/V2H(P) SoC. > > Signed-off-by: Lad Prabhakar > --- > v3->v4 > - Appended the interrupts instead of adding SoC specific > - Added restriction for clocks and reset Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds