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[2001:14ba:a0c3:3a00::227]) by smtp.gmail.com with ESMTPSA id e21-20020a2ea555000000b002d70a040f21sm35241ljn.91.2024.04.17.16.49.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Apr 2024 16:49:29 -0700 (PDT) Date: Thu, 18 Apr 2024 02:49:28 +0300 From: Dmitry Baryshkov To: Konrad Dybcio Cc: Bjorn Andersson , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong Subject: Re: [PATCH v2 7/7] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Message-ID: References: <20240404-topic-smem_speedbin-v2-0-c84f820b7e5b@linaro.org> <20240404-topic-smem_speedbin-v2-7-c84f820b7e5b@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240404-topic-smem_speedbin-v2-7-c84f820b7e5b@linaro.org> On Wed, Apr 17, 2024 at 10:02:59PM +0200, Konrad Dybcio wrote: > Add the speedbin masks to ensure only the desired OPPs are available on > chips of a given bin. > > Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. > > Signed-off-by: Konrad Dybcio > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- > 1 file changed, 20 insertions(+), 1 deletion(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry