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Message-ID: <eaf74619-1732-2b78-007f-3303f7fb1d3d@quicinc.com>
Date: Thu, 18 Apr 2024 13:04:25 +0530
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Subject: Re: [PATCH V3 3/5] arm64: dts: qcom: x1e80100: Resize GIC
 Redistributor register region
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To: Bjorn Andersson <quic_bjorande@quicinc.com>
CC: <sudeep.holla@arm.com>, <cristian.marussi@arm.com>, <andersson@kernel.org>,
        <konrad.dybcio@linaro.org>, <jassisinghbrar@gmail.com>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <dmitry.baryshkov@linaro.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <quic_rgottimu@quicinc.com>, <quic_kshivnan@quicinc.com>,
        <conor+dt@kernel.org>, <quic_gkohli@quicinc.com>,
        <quic_nkela@quicinc.com>, <quic_psodagud@quicinc.com>
References: <20240417132856.1106250-1-quic_sibis@quicinc.com>
 <20240417132856.1106250-4-quic_sibis@quicinc.com>
 <ZiA3f58OWfe5xf1f@hu-bjorande-lv.qualcomm.com>
From: Sibi Sankar <quic_sibis@quicinc.com>
In-Reply-To: <ZiA3f58OWfe5xf1f@hu-bjorande-lv.qualcomm.com>
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On 4/18/24 02:26, Bjorn Andersson wrote:
> On Wed, Apr 17, 2024 at 06:58:54PM +0530, Sibi Sankar wrote:
>> Resize the GICR register region as it currently seeps into the CPU Control
>> Processor mailbox RX region.
>>
> 
> Not that anyone is running a stable kernel here, but please make a habit
> of adding Fixes: tags when correcting previous mistakes.

Yeah, skipped adding fixed for ^^ reason but I'll add it in the next re-
spin.

> 
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
>> ---
>>
>> v2:
>> * Pickup Rb from Dimitry.
>>
>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index f5a3b39ae70e..28f65296781d 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -4949,7 +4949,7 @@ apps_smmu: iommu@15000000 {
>>   		intc: interrupt-controller@17000000 {
>>   			compatible = "arm,gic-v3";
>>   			reg = <0 0x17000000 0 0x10000>,     /* GICD */
>> -			      <0 0x17080000 0 0x480000>;    /* GICR * 12 */
>> +			      <0 0x17080000 0 0x380000>;    /* GICR * 12 */
>>   
> 
> The 12th GICR ends a bit before that, and per your commit message you're
> just nudging it down to get this range out of the say of your other
> range - rather than giving it a proper value.
> 
> Wouldn't 0x300000 be a better value here? Or am I perhaps missing

Yes, my calc was incorrect. It should be 0x300000.

-Sibi

> something in the difference? If so, I'd like the commit message to state
> what, so someone doesn't get excited and correct/break it later.
> 
> Regards,
> Bjorn
> 
>>   			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>>   
>> -- 
>> 2.34.1
>>