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[209.85.128.169]) by smtp.gmail.com with ESMTPSA id id8-20020a05690c680800b0061adccb38ecsm263514ywb.10.2024.04.18.02.48.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Apr 2024 02:48:41 -0700 (PDT) Received: by mail-yw1-f169.google.com with SMTP id 00721157ae682-617e6c873f3so6295327b3.2; Thu, 18 Apr 2024 02:48:41 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCXBkNAEDecr/0Ur8X20cuCZ1zwo53vsVh6DvwBlGZpBfpsvM7Xr2ZdewjCXbjs/8VGSJDnqMtWSmOupeZCT8nGco6X+lqlkzW0tr0tU0nEnVEwQIuTbOGbf47desZFvMUpPNhdJeJ47RtPFiXS9I3+vA+GpUAJN1PUfGvkMAyBrvizmYdkMc7wAnXHBAG4PuI+PYnn8FbsZFdv8Xrj1YGkn1adH X-Received: by 2002:a05:690c:d18:b0:61a:af67:1cfd with SMTP id cn24-20020a05690c0d1800b0061aaf671cfdmr2156849ywb.5.1713433720901; Thu, 18 Apr 2024 02:48:40 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240415-rzn1-gmac1-v3-0-ab12f2c4401d@bootlin.com> <20240415-rzn1-gmac1-v3-5-ab12f2c4401d@bootlin.com> In-Reply-To: <20240415-rzn1-gmac1-v3-5-ab12f2c4401d@bootlin.com> From: Geert Uytterhoeven Date: Thu, 18 Apr 2024 11:48:29 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH net-next v3 5/5] ARM: dts: r9a06g032: describe GMAC1 To: Romain Gantois Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Russell King , =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Thomas Petazzoni , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Romain, On Mon, Apr 15, 2024 at 11:18=E2=80=AFAM Romain Gantois wrote: > From: Cl=C3=A9ment L=C3=A9ger > > The r9a06g032 SoC of the RZ/N1 family features two GMAC devices named > GMAC1/2, that are based on Synopsys cores. GMAC1 is connected to a > RGMII/RMII converter that is already described in this device tree. > > Signed-off-by: "Cl=C3=A9ment L=C3=A9ger" > [rgantois: commit log] > Signed-off-by: Romain Gantois Thanks for your patch! > --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi > @@ -316,6 +316,25 @@ dma1: dma-controller@40105000 { > data-width =3D <8>; > }; > > + gmac1: ethernet@44000000 { > + compatible =3D "renesas,r9a06g032-gmac", "renesas= ,rzn1-gmac", "snps,dwmac"; > + reg =3D <0x44000000 0x2000>; > + interrupt-parent =3D <&gic>; The surrounding "soc" node already specifies the interrupt parent, so there is no need to repeat that. I could fix that while applying to renesas-devel for v6.10, but it looks like there will be a v4 for the rest of the series anyway? The rest LGTM, so with the above fixed: Reviewed-by: Geert Uytterhoeven > + interrupts =3D , > + , > + ; > + interrupt-names =3D "macirq", "eth_wake_irq", "et= h_lpi"; > + clocks =3D <&sysctrl R9A06G032_HCLK_GMAC0>; > + clock-names =3D "stmmaceth"; > + power-domains =3D <&sysctrl>; > + snps,multicast-filter-bins =3D <256>; > + snps,perfect-filter-entries =3D <128>; > + tx-fifo-depth =3D <2048>; > + rx-fifo-depth =3D <4096>; > + pcs-handle =3D <&mii_conv1>; > + status =3D "disabled"; > + }; > + > gmac2: ethernet@44002000 { > compatible =3D "renesas,r9a06g032-gmac", "renesas= ,rzn1-gmac", "snps,dwmac"; > reg =3D <0x44002000 0x2000>; > Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds