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Message-ID: <132c1e03-f55c-46ba-8a22-9cea1ebdfae1@linaro.org>
Date: Thu, 18 Apr 2024 11:57:35 +0200
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Subject: Re: [PATCH v2 6/7] drm/msm/adreno: Redo the speedbin assignment
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Bjorn Andersson <andersson@kernel.org>, Rob Clark <robdclark@gmail.com>,
 Abhinav Kumar <quic_abhinavk@quicinc.com>, Sean Paul <sean@poorly.run>,
 Marijn Suijten <marijn.suijten@somainline.org>,
 David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
 Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,
 Conor Dooley <conor+dt@kernel.org>, linux-arm-msm@vger.kernel.org,
 linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
 freedreno@lists.freedesktop.org, devicetree@vger.kernel.org,
 Neil Armstrong <neil.armstrong@linaro.org>
References: <20240404-topic-smem_speedbin-v2-0-c84f820b7e5b@linaro.org>
 <20240404-topic-smem_speedbin-v2-6-c84f820b7e5b@linaro.org>
 <rilfqdvei26bjyz76hdsh5wlh4s2lcn235up2vxbs65pnolyty@rs77jbxxqzye>
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From: Konrad Dybcio <konrad.dybcio@linaro.org>
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On 18.04.2024 1:49 AM, Dmitry Baryshkov wrote:
> On Wed, Apr 17, 2024 at 10:02:58PM +0200, Konrad Dybcio wrote:
>> There is no need to reinvent the wheel for simple read-match-set logic.
>>
>> Make speedbin discovery and assignment generation independent.
>>
>> This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx,
>> which has no representation in hardware whatshowever.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---

[...]

>> +	/* No speedbins defined for this GPU SKU => allow all defined OPPs */
>> +	if (!info->speedbins) {
>> +		adreno_gpu->speedbin = ADRENO_SPEEDBIN_FUSE_NODATA;
>> +		return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
> 
> BIT(0)

You mean for &supp_hw, or "1"?

1 is the "count" parameter, supp_hw is a "u32 supported_hw[count]"

> 
>> +	}
>> +
>> +	/*
>> +	 * If a real error (not counting older devicetrees having no nvmem references)
>> +	 * occurs when trying to get the fuse value, bail out.
>> +	 */
>> +	ret = adreno_read_speedbin(adreno_gpu, dev, &fuse);
>> +	if (ret) {
>> +		return ret;
>> +	} else if (fuse == ADRENO_SPEEDBIN_FUSE_NODATA) {
>> +		/* The info struct has speedbin data, but the DT is too old => allow all OPPs */
> 
> Missing assignment to adeno_gpu->speedbin ? Or is it fine?

Good catch. Only mesa (and I suppose you :D) read this value.

> 
>> +		DRM_DEV_INFO(dev, "No GPU speed bin fuse, please update your device tree\n");
>> +		return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
> 
> BIT(0)
> maybe #define it?

(ditto)

Konrad