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From: Xu Lu <luxu.kernel@bytedance.com>
Date: Thu, 18 Apr 2024 20:44:28 +0800
Message-ID: <CAPYmKFsQQPCd-34GArHfC-Sv8PCYHgmZxprK3WHKnJquQDoXiQ@mail.gmail.com>
Subject: Re: [External] Re: [RFC 0/2] riscv: Idle thread using Zawrs extension
To: =?UTF-8?Q?Christoph_M=C3=BCllner?= <christoph.muellner@vrull.eu>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, 
	andy.chiu@sifive.com, guoren@kernel.org, linux-riscv@lists.infradead.org, 
	linux-kernel@vger.kernel.org, lihangjing@bytedance.com, 
	dengliang.1214@bytedance.com, xieyongji@bytedance.com, 
	chaiwen.cc@bytedance.com, Andrew Jones <ajones@ventanamicro.com>, 
	Conor Dooley <conor.dooley@microchip.com>
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On Thu, Apr 18, 2024 at 8:26=E2=80=AFPM Christoph M=C3=BCllner
<christoph.muellner@vrull.eu> wrote:
>
> On Thu, Apr 18, 2024 at 1:50=E2=80=AFPM Xu Lu <luxu.kernel@bytedance.com>=
 wrote:
> >
> > This patch series introduces a new implementation of idle thread using
> > Zawrs extension.
>
> This overlaps with the following series:
>   https://lore.kernel.org/all/20240315134009.580167-7-ajones@ventanamicro=
com/

Hi Christoph.
Thanks for your reply!
Actually our patch series is different from this. The work from your
link focuses on providing support for Zawrs and implementing spinlock
using it, while our work focuses on implementing idle thread using
Zawrs and accelerating IPI to idle cpu. Of course, the ISA ZAWRS
config part can be merged. We will refine our code in the next version
to reduce code conflicts.

>
> BR
> Christoph
>
> >
> > The Zawrs[0] extension introduces two new instructions named WRS.STO an=
d
> > WRS.NTO in RISC-V. When software registers a reservation set using LR
> > instruction, a subsequent WRS.STO or WRS.NTO instruction will cause the
> > hart to stall in a low-power state until a store happens to the
> > reservation set or an interrupt becomes pending. The difference between
> > these two instructions is that WRS.STO will terminate stall after an
> > implementation-defined timeout while WRS.NTO won't.
> >
> > This patch series implements idle thread using WRS.NTO instruction.
> > Besides, we found there is no need to send a real IPI to wake up an idl=
e
> > CPU. Instead, we write IPI information to the reservation set of an idl=
e
> > CPU to wake it up and let it handle IPI quickly, without going through
> > tranditional interrupt handling routine.
> >
> > [0] https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
> >
> > Xu Lu (2):
> >   riscv: process: Introduce idle thread using Zawrs extension
> >   riscv: Use Zawrs to accelerate IPI to idle cpu
> >
> >  arch/riscv/Kconfig                 |  24 +++++++
> >  arch/riscv/include/asm/cpuidle.h   |  11 +---
> >  arch/riscv/include/asm/hwcap.h     |   1 +
> >  arch/riscv/include/asm/processor.h |  31 +++++++++
> >  arch/riscv/include/asm/smp.h       |  14 ++++
> >  arch/riscv/kernel/cpu.c            |   5 ++
> >  arch/riscv/kernel/cpufeature.c     |   1 +
> >  arch/riscv/kernel/process.c        | 102 ++++++++++++++++++++++++++++-
> >  arch/riscv/kernel/smp.c            |  39 +++++++----
> >  9 files changed, 205 insertions(+), 23 deletions(-)
> >
> > --
> > 2.20.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv