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From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: Thu, 18 Apr 2024 17:11:09 +0200
Message-ID: <CAMuHMdW7kiSYm8n8CfMs9zKaN+PhVt+=16nx=ttLk6Ur_jOa-g@mail.gmail.com>
Subject: Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Magnus Damm <magnus.damm@gmail.com>, Paul Walmsley <paul.walmsley@sifive.com>, 
	Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, linux-kernel@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, 
	linux-riscv@lists.infradead.org, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Prabhakar,

On Wed, Apr 3, 2024 at 10:36=E2=80=AFPM Prabhakar <prabhakar.csengg@gmail.c=
om> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared
> to the RZ/G2L (family) SoC.
>
> Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC
> controller driver. Two new registers, IMSK and TMSK, are defined to
> handle masking on RZ/Five SoC. The implementation utilizes a new data
> structure, `struct rzg2l_irqc_data`, to determine mask support for a
> specific controller instance.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - Added IRQCHIP_MATCH() for RZ/Five
> - Retaining a copy of OF data in priv
> - Rebased the changes

Thanks for the update!

> --- a/drivers/irqchip/irq-renesas-rzg2l.c
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -37,6 +37,8 @@
>  #define TSSEL_SHIFT(n)                 (8 * (n))
>  #define TSSEL_MASK                     GENMASK(7, 0)
>  #define IRQ_MASK                       0x3
> +#define IMSK                           0x10010
> +#define TMSK                           0x10020
>
>  #define TSSR_OFFSET(n)                 ((n) % 4)
>  #define TSSR_INDEX(n)                  ((n) / 4)
> @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
>         u32     titsr[2];
>  };
>
> +/**
> + * struct rzg2l_irqc_of_data - OF data structure
> + * @mask_supported: Indicates if mask registers are available
> + */
> +struct rzg2l_irqc_of_data {
> +       bool    mask_supported;
> +};
> +
>  /**
>   * struct rzg2l_irqc_priv - IRQ controller private data structure
>   * @base:      Controller's base address
> + * @data:      OF data pointer
>   * @fwspec:    IRQ firmware specific data
>   * @lock:      Lock to serialize access to hardware registers
>   * @cache:     Registers cache for suspend/resume
>   */
>  static struct rzg2l_irqc_priv {
>         void __iomem                    *base;
> +       const struct rzg2l_irqc_of_data *data;

That's not a copy, but a pointer.

>         struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
>         raw_spinlock_t                  lock;
>         struct rzg2l_irqc_reg_cache     cache;
> @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
>         irq_chip_eoi_parent(d);
>  }
>
> +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> +                                         unsigned int hwirq)
> +{
> +       u32 imsk =3D readl_relaxed(priv->base + IMSK);
> +       u32 bit =3D BIT(hwirq - IRQC_IRQ_START);
> +
> +       writel_relaxed(imsk | bit, priv->base + IMSK);
> +}
> +
> +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv=
,
> +                                           unsigned int hwirq)
> +{
> +       u32 imsk =3D readl_relaxed(priv->base + IMSK);
> +       u32 bit =3D BIT(hwirq - IRQC_IRQ_START);
> +
> +       writel_relaxed(imsk & ~bit, priv->base + IMSK);
> +}
> +
> +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> +                                          unsigned int hwirq)
> +{
> +       u32 tmsk =3D readl_relaxed(priv->base + TMSK);
> +       u32 bit =3D BIT(hwirq - IRQC_TINT_START);
> +
> +       writel_relaxed(tmsk | bit, priv->base + TMSK);
> +}
> +
> +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *pri=
v,
> +                                            unsigned int hwirq)
> +{
> +       u32 tmsk =3D readl_relaxed(priv->base + TMSK);
> +       u32 bit =3D BIT(hwirq - IRQC_TINT_START);
> +
> +       writel_relaxed(tmsk & ~bit, priv->base + TMSK);
> +}
> +
> +/* Must be called while priv->lock is held */
> +static void rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned =
int hwirq)
> +{
> +       if (!priv->data->mask_supported)
> +               return;
> +
> +       if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT)
> +               rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> +       else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> +               rzg2l_irqc_mask_tint_interrupt(priv, hwirq);
> +}
> +
> +static void rzg2l_irqc_mask(struct irq_data *d)
> +{
> +       struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d);
> +
> +       raw_spin_lock(&priv->lock);
> +       rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> +       raw_spin_unlock(&priv->lock);
> +       irq_chip_mask_parent(d);
> +}
> +
> +/* Must be called while priv->lock is held */
> +static void rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigne=
d int hwirq)
> +{
> +       if (!priv->data->mask_supported)
> +               return;
> +
> +       if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT)
> +               rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> +       else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> +               rzg2l_irqc_unmask_tint_interrupt(priv, hwirq);
> +}
> +
> +static void rzg2l_irqc_unmask(struct irq_data *d)
> +{
> +       struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d);
> +
> +       raw_spin_lock(&priv->lock);
> +       rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> +       raw_spin_unlock(&priv->lock);
> +       irq_chip_unmask_parent(d);
> +}
> +
>  static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
>  {
> +       struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d);
>         unsigned int hw_irq =3D irqd_to_hwirq(d);
>
>         if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> -               struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d);
>                 u32 offset =3D hw_irq - IRQC_TINT_START;
>                 u32 tssr_offset =3D TSSR_OFFSET(offset);
>                 u8 tssr_index =3D TSSR_INDEX(offset);
>                 u32 reg;
>
>                 raw_spin_lock(&priv->lock);
> +               if (enable)
> +                       rzg2l_irqc_unmask_once(priv, hw_irq);
> +               else
> +                       rzg2l_irqc_mask_once(priv, hw_irq);

You already know this is a TINT interrupt, so you could call
rzg2l_irqc_(un)mask_irq_interrupt() directly.

>                 reg =3D readl_relaxed(priv->base + TSSR(tssr_index));
>                 if (enable)
>                         reg |=3D TIEN << TSSEL_SHIFT(tssr_offset);
> @@ -157,6 +253,13 @@ static void rzg2l_tint_irq_endisable(struct irq_data=
 *d, bool enable)
>                         reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset));
>                 writel_relaxed(reg, priv->base + TSSR(tssr_index));
>                 raw_spin_unlock(&priv->lock);
> +       } else {
> +               raw_spin_lock(&priv->lock);
> +               if (enable)
> +                       rzg2l_irqc_unmask_once(priv, hw_irq);
> +               else
> +                       rzg2l_irqc_mask_once(priv, hw_irq);

Likewise.

> +               raw_spin_unlock(&priv->lock);
>         }
>  }

Gr{oetje,eeting}s,

                        Geert

--=20
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k=
org

In personal conversations with technical people, I call myself a hacker. Bu=
t
when I'm talking to journalists I just say "programmer" or something like t=
hat.
                                -- Linus Torvalds