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Thu, 18 Apr 2024 15:49:28 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 18 Apr 2024 08:49:27 -0700 Date: Thu, 18 Apr 2024 08:49:26 -0700 From: Bjorn Andersson To: Sibi Sankar CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH V3 2/5] mailbox: Add support for QTI CPUCP mailbox controller Message-ID: References: <20240417132856.1106250-1-quic_sibis@quicinc.com> <20240417132856.1106250-3-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VfKhppR1wgkYFVVoSwLUFTIakXyyUK0s X-Proofpoint-ORIG-GUID: VfKhppR1wgkYFVVoSwLUFTIakXyyUK0s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-18_13,2024-04-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 phishscore=0 mlxlogscore=860 bulkscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404180112 On Thu, Apr 18, 2024 at 01:01:50PM +0530, Sibi Sankar wrote: > On 4/18/24 02:56, Bjorn Andersson wrote: > > On Wed, Apr 17, 2024 at 06:58:53PM +0530, Sibi Sankar wrote: > > > diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c [..] > > > > > + if (status & BIT(i)) { > > > > Can't you combine the for loop and this conditional into a > > for_each_bit_set()? > > The only drawback I see here is if the number of channels increase to > it's full capacity of 64 since for_each_set_bit expects unsigned long. > It takes a unsigned long * and it can take a size > BITS_PER_LONG. But I've not convinced myself that the bit order across two of those matches the u64 bits. > > > > > + val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); > > > + chan = &cpucp->chans[i]; > > > + spin_lock_irqsave(&chan->lock, flags); > > > > Can you please add a comment here to document that the lock is taken > > here to deal with races against client registration? (It wasn't obvious > > to me...) > > This is was put in to handle irqs after channel closure. Meaning we > don't want to send data on a closed/empty channel. > You're dealing with that through the chan->cl check below, not the lock itself. So the lock here would be for synchronizing this code with potentially concurrent execution of __mbox_bind_client() or e.g. mbox_free_channel(). But if this is indeed the problem, then we're locking here to ensure that mbox_chan_received_data() will not dereference chan->cl while it's being modified elsewhere int he mailbox core. If that's the case, I think this needs to be strongly documented in the API, or perhaps better yet the lock being moved into mbox_chan_received_data(). Regards, Bjorn