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Date: Thu, 18 Apr 2024 21:00:01 +0100
From: Conor Dooley <conor@kernel.org>
To: Eric Biggers <ebiggers@kernel.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
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	=?iso-8859-1?Q?Cl=E9ment_L=E9ger?= <cleger@rivosinc.com>,
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	Jerry Shih <jerry.shih@sifive.com>
Subject: Re: [PATCH v4 7/9] riscv: vector: adjust minimum Vector requirement
 to ZVE32X
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On Thu, Apr 18, 2024 at 11:41:29AM -0700, Eric Biggers wrote:

> If the RISC-V kernel ever disables V, then it should also disable everyth=
ing
> that depends on V.
>=20
> This would be similar to how on x86, if the kernel decides to disable AVX=
 to
> mitigate the Gather Data Sampling vulnerability, it also disables AVX2, A=
VX512,
> VAES, VPCLMULQDQ, etc.  See cpuid_deps[] in arch/x86/kernel/cpu/cpuid-dep=
s.c.
>=20
> Sometimes CPU features depend on other ones.  That's just the way things =
work.

=F0=9F=A4=A8

> Whenever possible that should be handled centrally, not pushed down to ev=
ery
> user both in-kernel and userspace.

FWIW, anything detected but rejected while probing the DT or ACPI tables
will cause riscv_isa_extension_available() (or other APIs) to return false.


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