Received-SPF: pass (google.com: domain of linux-kernel+bounces-150838-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223;
Precedence: bulk
MIME-Version: 1.0
References: <20240405124348.27644-1-puranjay12@gmail.com> <CAEf4BzZ2Tz5-GwbQKYg7KoGwqN8ewPBakmghHaH20MfoATe74g@mail.gmail.com>
 <87cyr0uwsg.fsf@all.your.base.are.belong.to.us>
In-Reply-To: <87cyr0uwsg.fsf@all.your.base.are.belong.to.us>
From: Andrii Nakryiko <andrii.nakryiko@gmail.com>
Date: Thu, 18 Apr 2024 15:24:11 -0700
Message-ID: <CAEf4BzahfDssv6SgKYmay+CxQ7GAY9TD5LPG8D9NjGrzMBY28Q@mail.gmail.com>
Subject: Re: [PATCH bpf-next] riscv, bpf: add internal-only MOV instruction to
 resolve per-CPU addrs
To: =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>
Cc: Puranjay Mohan <puranjay12@gmail.com>, Alexei Starovoitov <ast@kernel.org>, 
	Daniel Borkmann <daniel@iogearbox.net>, Andrii Nakryiko <andrii@kernel.org>, 
	Martin KaFai Lau <martin.lau@linux.dev>, Eduard Zingerman <eddyz87@gmail.com>, Song Liu <song@kernel.org>, 
	Yonghong Song <yonghong.song@linux.dev>, John Fastabend <john.fastabend@gmail.com>, 
	KP Singh <kpsingh@kernel.org>, Stanislav Fomichev <sdf@google.com>, Hao Luo <haoluo@google.com>, 
	Jiri Olsa <jolsa@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, 
	Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, bpf@vger.kernel.org, 
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, 
	Pu Lehui <pulehui@huawei.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Mon, Apr 8, 2024 at 12:40=E2=80=AFAM Bj=C3=B6rn T=C3=B6pel <bjorn@kernel=
org> wrote:
>
> Andrii Nakryiko <andrii.nakryiko@gmail.com> writes:
>
> > On Fri, Apr 5, 2024 at 5:44=E2=80=AFAM Puranjay Mohan <puranjay12@gmail=
com> wrote:
> >>
> >> Support an instruction for resolving absolute addresses of per-CPU
> >> data from their per-CPU offsets. This instruction is internal-only and
> >> users are not allowed to use them directly. They will only be used for
> >> internal inlining optimizations for now between BPF verifier and BPF
> >> JITs.
> >>
> >> RISC-V uses generic per-cpu implementation where the offsets for CPUs
> >> are kept in an array called __per_cpu_offset[cpu_number]. RISCV stores
> >> the address of the task_struct in TP register. The first element in
> >> tast_struct is struct thread_info, and we can get the cpu number by
> >> reading from the TP register + offsetof(struct thread_info, cpu).
> >>
> >> Once we have the cpu number in a register we read the offset for that
> >> cpu from address: &__per_cpu_offset + cpu_number << 3. Then we add thi=
s
> >> offset to the destination register.
> >>
> >> To measure the improvement from this change, the benchmark in [1] was
> >> used on Qemu:
> >>
> >> Before:
> >> glob-arr-inc   :    1.127 =C2=B1 0.013M/s
> >> arr-inc        :    1.121 =C2=B1 0.004M/s
> >> hash-inc       :    0.681 =C2=B1 0.052M/s
> >>
> >> After:
> >> glob-arr-inc   :    1.138 =C2=B1 0.011M/s
> >> arr-inc        :    1.366 =C2=B1 0.006M/s
> >> hash-inc       :    0.676 =C2=B1 0.001M/s
> >
> > TBH, I don't trust benchmarks done inside QEMU. Can you try running
> > this on some real hardware?
>
> I just ran it on a "VisionFive2" SBC:
>
> BEFORE
> =3D=3D=3D=3D=3D=3D
> glob-arr-inc   :   11.586 =C2=B1 0.021M/s
> arr-inc        :   10.892 =C2=B1 0.005M/s
> hash-inc       :    1.517 =C2=B1 0.001M/s
>
> AFTER
> =3D=3D=3D=3D=3D
> glob-arr-inc   :   11.893 =C2=B1 0.017M/s  (+2.6%)
> arr-inc        :   11.630 =C2=B1 0.020M/s  (+6.8%)
> hash-inc       :    1.543 =C2=B1 0.002M/s  (+1.7%)
>

Nice, looks pretty reasonable (and especially if
bpf_smp_get_current_id() gets inlined as well, the numbers should be
even better)


> (It's early, and the coffee haven't kicked in, so I hope the
> calculations are correct...)
>
> >>
> >> [1] https://github.com/anakryiko/linux/commit/8dec900975ef
> >>
> >> Signed-off-by: Puranjay Mohan <puranjay12@gmail.com>
> >> ---
> >>  arch/riscv/net/bpf_jit_comp64.c | 24 ++++++++++++++++++++++++
> >>  1 file changed, 24 insertions(+)
> >>
> >> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_=
comp64.c
> >> index 15e482f2c657..e95bd1d459a4 100644
> >> --- a/arch/riscv/net/bpf_jit_comp64.c
> >> +++ b/arch/riscv/net/bpf_jit_comp64.c
> >> @@ -12,6 +12,7 @@
> >>  #include <linux/stop_machine.h>
> >>  #include <asm/patch.h>
> >>  #include <asm/cfi.h>
> >> +#include <asm/percpu.h>
> >>  #include "bpf_jit.h"
> >>
> >>  #define RV_FENTRY_NINSNS 2
> >> @@ -1089,6 +1090,24 @@ int bpf_jit_emit_insn(const struct bpf_insn *in=
sn, struct rv_jit_context *ctx,
> >>                         emit_or(RV_REG_T1, rd, RV_REG_T1, ctx);
> >>                         emit_mv(rd, RV_REG_T1, ctx);
> >>                         break;
> >> +               } else if (insn_is_mov_percpu_addr(insn)) {
> >> +                       if (rd !=3D rs)
> >> +                               emit_mv(rd, rs, ctx);
> >
> > Is this an unconditional move instruction? in x86-64, EMIT_mov checks
> > whether source and destination registers are the same and doesn't emit
> > anything if they match (which makes sense, right)?
>
> Yeah, it is. Folding the check into the emit sounds like a good idea.
>

great

>
> Bj=C3=B6rn