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Message-ID: <1583360debaee14a988e4019cf30250f6eb4d8da.camel@codeconstruct.com.au>
Subject: Re: [PATCH] peci: aspeed: Clear clock_divider value before setting
 it
From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: "Winiarska, Iwona" <iwona.winiarska@intel.com>, 
	"linux-aspeed@lists.ozlabs.org"
	 <linux-aspeed@lists.ozlabs.org>, "linux-arm-kernel@lists.infradead.org"
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Cc: "billy_tsai@aspeedtech.com" <billy_tsai@aspeedtech.com>
Date: Fri, 19 Apr 2024 08:55:51 +0930
In-Reply-To: <7520ac6ef7afae66f9b1636e5806ff2bfd93584d.camel@intel.com>
References: <20240417134849.5793-1-iwona.winiarska@intel.com>
	 <7b0ef5c90138e8c1d1829de249a480709170141b.camel@codeconstruct.com.au>
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On Thu, 2024-04-18 at 13:41 +0000, Winiarska, Iwona wrote:
> On Thu, 2024-04-18 at 09:11 +0930, Andrew Jeffery wrote:
> > Hi Iwona,
> >=20
> > On Wed, 2024-04-17 at 15:48 +0200, Iwona Winiarska wrote:
> > > PECI clock divider is programmed on 10:8 bits of PECI Control registe=
r.
> > > Before setting a new value, clear bits read from hardware.
> > >=20
> > > Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
> >=20
> > I think it would be best to add a Fixes: tag and Cc: stable in
> > accordance with the stable tree rules. Are you happy to do so?
>=20
> Hi!
>=20
> Technically, the initial value of this register should be 0, but I've add=
ed the
> clear just to be on the safe side and to not have to rely on that.

Yeah, it could cause havoc with an unbind/bind sequence if people are
messing with the clocks in between.

> I don't think we're ever programming invalid values in the real-world sce=
narios,
> and because of that - I don't think this is stable material.

Right, I don't expect people are doing the above in environments where
stability is a concern.

Thanks for elaborating.

Andrew