Received-SPF: pass (google.com: domain of linux-kernel+bounces-150901-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223;
Date: Fri, 19 Apr 2024 09:19:29 +0800
From: Yan Zhao <yan.y.zhao@intel.com>
To: <isaku.yamahata@intel.com>
CC: <kvm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<isaku.yamahata@gmail.com>, Paolo Bonzini <pbonzini@redhat.com>,
	<erdemaktas@google.com>, Sean Christopherson <seanjc@google.com>, Sagi Shahar
	<sagis@google.com>, Kai Huang <kai.huang@intel.com>, <chen.bo@intel.com>,
	<hang.yuan@intel.com>, <tina.zhang@intel.com>
Subject: Re: [PATCH v19 010/130] KVM: x86: Pass is_private to gmem hook of
 gmem_max_level
Message-ID: <ZiHGoUUcGlZObQvx@yzhao56-desk.sh.intel.com>
Reply-To: Yan Zhao <yan.y.zhao@intel.com>
References: <cover.1708933498.git.isaku.yamahata@intel.com>
 <8108cc2b8ff01ec22de68f0d0758ef0671db43fc.1708933498.git.isaku.yamahata@intel.com>
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <8108cc2b8ff01ec22de68f0d0758ef0671db43fc.1708933498.git.isaku.yamahata@intel.com>
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?npuQps64/wUWKsTtgbK4SEu3fTTGfjw6HN1NMSkDobk6eOVyJoQl770EBfWj?=
 =?us-ascii?Q?XmZOZ8Ev9n5A/k4G+LI6juaubCyz1M+ByHxkNlhdo+P1XkP/yr8OPsToAgJ/?=
 =?us-ascii?Q?tZJCyDLYaXaAomUThsMVUiOHLGy/mewez7QEpKtM4mEgKh3bAflvGQ/uESI2?=
 =?us-ascii?Q?/78jGNPbijoTVJk95yuarYDTFkKUvmA7w0pbCg0PWWhL641xt8VKQqp8gbfl?=
 =?us-ascii?Q?024ncfYodtJ9EeWJyHtYczl+RlnCoD+vtyH+U5TYEBURdmjhlY9st2k7VdWZ?=
 =?us-ascii?Q?u8Okc7qT5xTfI/daPVdzE6Oml5gcH9Jeduo5IGuWTG6/v/+Ex8X1+dJn/+ER?=
 =?us-ascii?Q?rjb81zyZES2zqFVMBthx85hMvZTIB/aVuB3DwrNr2bhYG9eYF9+LmVIbEHm6?=
 =?us-ascii?Q?ivkgwED+hXTdUh7FrtjfAuUPAHJ5Ky3V9HJvZ1KuyLXTAP0ESog2+12JcONV?=
 =?us-ascii?Q?V3cnEVuiOfbXVfRbmnDsjB2taIyVBwXXeuu59BLSc54cccHqwYRyQssZKMOK?=
 =?us-ascii?Q?5JB2TFs2psoZuG8LEvsVK08BruvTvAxgtYsXKjkS0EZ5Ropxz9RGfnE6aJEH?=
 =?us-ascii?Q?wKdHqxqrRFTZMUGS0Re6ivMX7/IDVETje4rfUgEXdK2sSu+wht4lohcRv5T5?=
 =?us-ascii?Q?mLwFFWFMCYWCRM6CqChfCr0TDAQmK7A9G+2ZmMZagYV60amgl3PwKNsy6rRS?=
 =?us-ascii?Q?SYe8wuUVexcXbq2E2ZGa5FcvZo/YhPiitiwgPbamelhV8MkZBFA0MgB0ilvL?=
 =?us-ascii?Q?64J3TK3ca82zdksvLSES0GVu8PrIkuTDlx8UxK9Wupcumb+1bWlVk/uFkghr?=
 =?us-ascii?Q?iPEWRklSfoAvSjVlnnxmf4D6me4MnJtwMASfxXcIMhBkgbXb48EACF0sCGfG?=
 =?us-ascii?Q?QlwCNFkZm4DzeXe8Tyh+EfHg6AfPkBUUojCX6NN1ZnZDaGq4JvDi1BoT0k0E?=
 =?us-ascii?Q?g4e7Lqx5dQXJRbOq2DBzB4VfoB/bwvtP1KO0kLwNDrG5TQ68qV/Zq0s+Yp/Z?=
 =?us-ascii?Q?YT9pQJVM5jbQq9EWhD8t7/X+Vq3oTTHaRKUEbf2k0Y/Igko/0LfeTXwTuQGF?=
 =?us-ascii?Q?tcwpVW9L5SxUiCGpsxWTAsXdDpiKRNP7oH8tjaccWUFOFW8xIhlhDynwF0Jc?=
 =?us-ascii?Q?LE0fo28p3Y+PwZGTMcnHUf/MudpGi1Q4zyHipZM6aZBVG8IzZacO9ffOClYE?=
 =?us-ascii?Q?bm2eQBOYSX5TXyKCdJ+O74S39cmPeyUl4LYWwI1c3APDgvh+BTqNWOlLkMhp?=
 =?us-ascii?Q?gHE9GDBRlibWVafoWT0OXUA/+dzlFkH3pQFErgWIPyWBVMtafN/y9lvFd+vI?=
 =?us-ascii?Q?WUYpS4GDmazshxlAL8SL1HfsH3bUZ3o2koagw5LoKipjfM4Pedk3ZnzUhXvu?=
 =?us-ascii?Q?tOxCbuQMolELlAG4hEMT2MfUhJzc3jBzrSCI7tgGnA7leL/YjJzpRlepnuSN?=
 =?us-ascii?Q?6DFjRYVaLXl0pTZtdglkEPzszZBmD6JrpcinZsdMTqgQ604FDxi0SUWLzmPT?=
 =?us-ascii?Q?yREofitk7vxE8iUYQoaWKvW3mYOtlknUA6gtJV1/qnnbf1TDIifSBjXxPo86?=
 =?us-ascii?Q?WGXodu7n5Dhk8BwNtkDL0Zzqd0nDB+1SNl2StwTw?=
X-MS-Exchange-CrossTenant-Network-Message-Id: 82acfa71-037b-4129-4679-08dc600ed553
X-MS-Exchange-CrossTenant-AuthSource: DS7PR11MB5966.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Apr 2024 01:20:00.5796
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: /JwphqgG1WDNznrxkrmYvzwedQdOuTkm74XhDyEv8N2NzZnmJdpTL5HDF4QueQ4XMO5YY69w8qd/uMSPsbHjDQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR11MB7450
X-OriginatorOrg: intel.com

On Mon, Feb 26, 2024 at 12:25:12AM -0800, isaku.yamahata@intel.com wrote:
> From: Isaku Yamahata <isaku.yamahata@intel.com>
> 
> TDX wants to know the faulting address is shared or private so that the max
> level is limited by Secure-EPT or not.  Because fault->gfn doesn't include
> shared bit, gfn doesn't tell if the faulting address is shared or not.
> Pass is_private for TDX case.
> 
> TDX logic will be if (!is_private) return 0; else return PG_LEVEL_4K.
> 
> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
> ---
>  arch/x86/include/asm/kvm_host.h | 3 ++-
>  arch/x86/kvm/mmu/mmu.c          | 3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index d15f5b4b1656..57ce89fc2740 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -1797,7 +1797,8 @@ struct kvm_x86_ops {
>  
>  	gva_t (*get_untagged_addr)(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags);
>  
> -	int (*gmem_max_level)(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, u8 *max_level);
> +	int (*gmem_max_level)(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn,
> +			      bool is_private, u8 *max_level);
>  };
>  
>  struct kvm_x86_nested_ops {
> diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> index 1e5e12d2707d..22db1a9f528a 100644
> --- a/arch/x86/kvm/mmu/mmu.c
> +++ b/arch/x86/kvm/mmu/mmu.c
> @@ -4324,7 +4324,8 @@ static int kvm_faultin_pfn_private(struct kvm_vcpu *vcpu,
>  
>  	max_level = kvm_max_level_for_order(max_order);
>  	r = static_call(kvm_x86_gmem_max_level)(vcpu->kvm, fault->pfn,
> -						fault->gfn, &max_level);
> +						fault->gfn, fault->is_private,
> +						&max_level);
fault->is_private is always true in kvm_faultin_pfn_private().
Besides, as shared page allocation will not go to kvm_faultin_pfn_private(),
why do we need to add the "is_private" parameter ?

>  	if (r) {
>  		kvm_release_pfn_clean(fault->pfn);
>  		return r;
> -- 
> 2.25.1
> 
>