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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: Fri, 19 Apr 2024 08:16:01 +0100
Message-ID: <CA+V-a8vA_7hJWBO3Lr4akZAoVS1V1qB8xZ1n8Sgs1EzXQpgReg@mail.gmail.com>
Subject: Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>, 
	Geert Uytterhoeven <geert+renesas@glider.be>, Thomas Gleixner <tglx@linutronix.de>, 
	Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, 
	Conor Dooley <conor+dt@kernel.org>, Magnus Damm <magnus.damm@gmail.com>, 
	Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, 
	Albert Ou <aou@eecs.berkeley.edu>, 
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, 
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, 
	"linux-renesas-soc@vger.kernel.org" <linux-renesas-soc@vger.kernel.org>, 
	"linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, 
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Geert,

On Thu, Apr 18, 2024 at 4:13=E2=80=AFPM Geert Uytterhoeven <geert@linux-m68=
k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Apr 4, 2024 at 3:35=E2=80=AFPM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Thu, Apr 4, 2024 at 2:31=E2=80=AFPM Biju Das <biju.das.jz@bp.renesas=
com> wrote:
> > > > -----Original Message-----
> > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > > > On Thu, Apr 4, 2024 at 8:44=E2=80=AFAM Biju Das <biju.das.jz@bp.ren=
esas.com> wrote:
> > > > > > -----Original Message-----
> > > > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) a=
s
> > > > > > compared to the RZ/G2L (family) SoC.
> > > > > >
> > > > > > Introduce masking/unmasking support for IRQ and TINT interrupts=
 in
> > > > > > IRQC controller driver. Two new registers, IMSK and TMSK, are
> > > > > > defined to handle masking on RZ/Five SoC. The implementation
> > > > > > utilizes a new data structure, `struct rzg2l_irqc_data`, to det=
ermine mask support for a
> > > > specific controller instance.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar
> > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > ---
> > > > > > v1->v2
> > > > > > - Added IRQCHIP_MATCH() for RZ/Five
> > > > > > - Retaining a copy of OF data in priv
> > > > > > - Rebased the changes
> > > > > > ---
> > > > > >  drivers/irqchip/irq-renesas-rzg2l.c | 137
> > > > > > +++++++++++++++++++++++++++-
> > > > > >  1 file changed, 132 insertions(+), 5 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > > b/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > > index f6484bf15e0b..6fa8d65605dc 100644
> > > > > > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > > @@ -37,6 +37,8 @@
> > > > > >  #define TSSEL_SHIFT(n)                       (8 * (n))
> > > > > >  #define TSSEL_MASK                   GENMASK(7, 0)
> > > > > >  #define IRQ_MASK                     0x3
> > > > > > +#define IMSK                         0x10010
> > > > > > +#define TMSK                         0x10020
> > > > > >
> > > > > >  #define TSSR_OFFSET(n)                       ((n) % 4)
> > > > > >  #define TSSR_INDEX(n)                        ((n) / 4)
> > > > > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> > > > > >       u32     titsr[2];
> > > > > >  };
> > > > > >
> > > > > > +/**
> > > > > > + * struct rzg2l_irqc_of_data - OF data structure
> > > > > > + * @mask_supported: Indicates if mask registers are available =
 */
> > > > > > +struct rzg2l_irqc_of_data {
> > > > > > +     bool    mask_supported;
> > > > > > +};
> > > > > > +
> > > > > >  /**
> > > > > >   * struct rzg2l_irqc_priv - IRQ controller private data struct=
ure
> > > > > >   * @base:    Controller's base address
> > > > > > + * @data:    OF data pointer
> > > > > >   * @fwspec:  IRQ firmware specific data
> > > > > >   * @lock:    Lock to serialize access to hardware registers
> > > > > >   * @cache:   Registers cache for suspend/resume
> > > > > >   */
> > > > > >  static struct rzg2l_irqc_priv {
> > > > > >       void __iomem                    *base;
> > > > > > +     const struct rzg2l_irqc_of_data *data;
> > > > > >       struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
> > > > > >       raw_spinlock_t                  lock;
> > > > > >       struct rzg2l_irqc_reg_cache     cache;
> > > > > > @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_da=
ta *d)
> > > > > >       irq_chip_eoi_parent(d);
> > > > > >  }
> > > > > >
> > > > > > +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_pr=
iv *priv,
> > > > > > +                                       unsigned int hwirq) {
> > > > > > +     u32 imsk =3D readl_relaxed(priv->base + IMSK);
> > > > > > +     u32 bit =3D BIT(hwirq - IRQC_IRQ_START);
> > > > > > +
> > > > > > +     writel_relaxed(imsk | bit, priv->base + IMSK); }
> > > > > > +
> > > > > > +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_=
priv *priv,
> > > > > > +                                         unsigned int hwirq) {
> > > > > > +     u32 imsk =3D readl_relaxed(priv->base + IMSK);
> > > > > > +     u32 bit =3D BIT(hwirq - IRQC_IRQ_START);
> > > > > > +
> > > > > > +     writel_relaxed(imsk & ~bit, priv->base + IMSK); }
> > > > > > +
> > > > > > +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_p=
riv *priv,
> > > > > > +                                        unsigned int hwirq) {
> > > > > > +     u32 tmsk =3D readl_relaxed(priv->base + TMSK);
> > > > > > +     u32 bit =3D BIT(hwirq - IRQC_TINT_START);
> > > > > > +
> > > > > > +     writel_relaxed(tmsk | bit, priv->base + TMSK); }
> > > > > > +
> > > > > > +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc=
_priv *priv,
> > > > > > +                                          unsigned int hwirq) =
{
> > > > > > +     u32 tmsk =3D readl_relaxed(priv->base + TMSK);
> > > > > > +     u32 bit =3D BIT(hwirq - IRQC_TINT_START);
> > > > > > +
> > > > > > +     writel_relaxed(tmsk & ~bit, priv->base + TMSK); }
> > > > > > +
> > > > > > +/* Must be called while priv->lock is held */ static void
> > > > > > +rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned in=
t
> > > > > > +hwirq) {
> > > > > > +     if (!priv->data->mask_supported)
> > > > > > +             return;
> > > > > > +
> > > > > > +     if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUN=
T)
> > > > > > +             rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> > > > > > +     else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_I=
RQ)
> > > > > > +             rzg2l_irqc_mask_tint_interrupt(priv, hwirq); }
> > > > > > +
> > > > > > +static void rzg2l_irqc_mask(struct irq_data *d) {
> > > > > > +     struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d);
> > > > > > +
> > > > > > +     raw_spin_lock(&priv->lock);
> > > > > > +     rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> > > > > > +     raw_spin_unlock(&priv->lock);
> > > > > > +     irq_chip_mask_parent(d);
> > > > > > +}
> > > > > > +
> > > > > > +/* Must be called while priv->lock is held */ static void
> > > > > > +rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned =
int
> > > > > > +hwirq) {
> > > > > > +     if (!priv->data->mask_supported)
> > > > > > +             return;
> > > > > > +
> > > > > > +     if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUN=
T)
> > > > > > +             rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> > > > > > +     else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_I=
RQ)
> > > > > > +             rzg2l_irqc_unmask_tint_interrupt(priv, hwirq); }
> > > > > > +
> > > > > > +static void rzg2l_irqc_unmask(struct irq_data *d) {
> > > > > > +     struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d);
> > > > > > +
> > > > > > +     raw_spin_lock(&priv->lock);
> > > > > > +     rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> > > > > > +     raw_spin_unlock(&priv->lock);
> > > > > > +     irq_chip_unmask_parent(d);
> > > > > > +}
> > > > > > +
> > > > > >  static void rzg2l_tint_irq_endisable(struct irq_data *d, bool
> > > > > > enable)  {
> > > > > > +     struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d);
> > > > > >       unsigned int hw_irq =3D irqd_to_hwirq(d);
> > > > > >
> > > > > >       if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)=
 {
> > > > > > -             struct rzg2l_irqc_priv *priv =3D irq_data_to_priv=
(d);
> > > > > >               u32 offset =3D hw_irq - IRQC_TINT_START;
> > > > > >               u32 tssr_offset =3D TSSR_OFFSET(offset);
> > > > > >               u8 tssr_index =3D TSSR_INDEX(offset);
> > > > > >               u32 reg;
> > > > > >
> > > > > >               raw_spin_lock(&priv->lock);
> > > > > > +             if (enable)
> > > > > > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > > > > > +             else
> > > > > > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > > > > >               reg =3D readl_relaxed(priv->base + TSSR(tssr_inde=
x));
> > > > > >               if (enable)
> > > > > >                       reg |=3D TIEN << TSSEL_SHIFT(tssr_offset)=
; @@
> > > > > > -157,6 +253,13 @@ static void rzg2l_tint_irq_endisable(struct i=
rq_data *d, bool enable)
> > > > > >                       reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offse=
t));
> > > > > >               writel_relaxed(reg, priv->base + TSSR(tssr_index)=
);
> > > > > >               raw_spin_unlock(&priv->lock);
> > > > > > +     } else {
> > > > > > +             raw_spin_lock(&priv->lock);
> > > > > > +             if (enable)
> > > > > > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > > > > > +             else
> > > > > > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > > > > > +             raw_spin_unlock(&priv->lock);
> > > > > >       }
> > > > > >  }
> > > > > >
> > > > > > @@ -324,8 +427,8 @@ static struct syscore_ops rzg2l_irqc_syscor=
e_ops
> > > > > > =3D {  static const struct irq_chip irqc_chip =3D {
> > > > > >       .name                   =3D "rzg2l-irqc",
> > > > > >       .irq_eoi                =3D rzg2l_irqc_eoi,
> > > > > > -     .irq_mask               =3D irq_chip_mask_parent,
> > > > > > -     .irq_unmask             =3D irq_chip_unmask_parent,
> > > > > > +     .irq_mask               =3D rzg2l_irqc_mask,
> > > > > > +     .irq_unmask             =3D rzg2l_irqc_unmask,
> > > > >
> > > > > I feel this will be clean, if we have
> > > > >
> > > > > static const struct irq_chip rzg2l_irqc_chip =3D {
> > > > >         .name                   =3D "rzg2l-irqc",
> > > > >         ...
> > > > >         .irq_mask               =3D irq_chip_mask_parent,
> > > > >         .irq_unmask             =3D irq_chip_unmask_parent,
> > > > >         ....
> > > > > };
> > > > >
> > > > > static const struct irq_chip rzfive_irqc_chip =3D {
> > > > >         .name                   =3D "rzfive-irqc",
> > > > >         ...
> > > > >         .irq_mask               =3D rzfive_irqc_mask,
> > > > >         .irq_unmask             =3D rzfive_irqc_unmask,
> > > > >         ....
> > > > > };
> > > > >
> > > > > And passing this in rzg2l_irqc_init() and rzfive_irqc_init(), see
> > > > > below
> > > > >
> > > > > return rzg2l_irqc_init_helper(node, parent, & rzg2l_irqc_chip); r=
eturn
> > > > > rzg2l_irqc_init_helper(node, parent, & rzfive_irqc_chip);
> > > > >
> > > > If we do the above we are stuck with "struct irq_chip" as data, for=
 further upcoming SoCs (for
> > > > example RZ/V2H) which have more features we need to pass custom dat=
a to handle these features.
> > >
> > > That time device data can be extended like below
> > >
> > > struct rz_g2l_irq_chip {
> > >         struct irq_chip;
> > >         void *data; /* custom data */
> > > }
> > >
> > Ok, but i'll wait for Geert to come back on this as Geert suggested to
> > me to do it this way.
>
> I agree with Biju.
>
> Having separate irq_chips lets us avoid taking the spinlock on RZ/G2L.
>
Agreed, I will add separate irq_chips.

Cheers,
Prabhakar