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Subject: RE: [PATCH]PCIE ASPM support - takes 3
Date: Fri, 25 Jan 2008 16:01:32 +0800
Message-ID: <FC1D1B23302A22499C60C967336B2AE0024F0A74@pdsmsx411.ccr.corp.intel.com>
In-Reply-To: <20080124172258.GA5447@ucw.cz>
Thread-Topic: [PATCH]PCIE ASPM support - takes 3
Thread-Index: AchfIrxIeAS6vWJrTea4Y44q0zyudgABYovA
References: <1200621388.8965.3.camel@sli10-desk.sh.intel.com> <20080124172258.GA5447@ucw.cz>
From: "Li, Shaohua" <shaohua.li@intel.com>
To: "Pavel Machek" <pavel@ucw.cz>
Cc: "lkml" <linux-kernel@vger.kernel.org>,
       "linux-pci" <linux-pci@atrey.karlin.mff.cuni.cz>,
       "Greg KH" <greg@kroah.com>,
       "Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com>,
       "Kok, Auke-jan H" <auke-jan.h.kok@intel.com>,
       "Matthew Wilcox" <matthew@wil.cx>
Sender: linux-kernel-owner@vger.kernel.org
Content-Length: 984
Lines: 28

>
>
>Hi!
>
>> v3->v2, fixed the issues Matthew Wilcox raised.
>>
>> PCI Express ASPM defines a protocol for PCI Express components in the
D0
>> state to reduce Link power by placing their Links into a low power
state
>> and instructing the other end of the Link to do likewise. This
>> capability allows hardware-autonomous, dynamic Link power reduction
>> beyond what is achievable by software-only controlled power
management.
>> However, The device should be configured by software appropriately.
>> Enabling ASPM will save power, but will introduce device latency.
>
>How big is the latency? 1msec? 10msec? 100usec?
Haven't accurate number, but in one device, it declaims L0s latency is <
128ns, L1 latency is < 64us.

Thanks,
Shaohua
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