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18 Apr 2024 19:33:40 -0700 Message-ID: Date: Fri, 19 Apr 2024 10:33:37 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v19 111/130] KVM: TDX: Implement callbacks for MSR operations for TDX To: isaku.yamahata@intel.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , Kai Huang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com References: <62f8890cb90e49a3e0b0d5946318c0267b80c540.1708933498.git.isaku.yamahata@intel.com> From: Binbin Wu In-Reply-To: <62f8890cb90e49a3e0b0d5946318c0267b80c540.1708933498.git.isaku.yamahata@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2/26/2024 4:26 PM, isaku.yamahata@intel.com wrote: > From: Isaku Yamahata > > Implements set_msr/get_msr/has_emulated_msr methods for TDX to handle > hypercall from guest TD for paravirtualized rdmsr and wrmsr. The TDX > module virtualizes MSRs. For some MSRs, it injects #VE to the guest TD > upon RDMSR or WRMSR. The exact list of such MSRs are defined in the spec. > > Upon #VE, the guest TD may execute hypercalls, > TDG.VP.VMCALL and TDG.VP.VMCALL, > which are defined in GHCI (Guest-Host Communication Interface) so that the > host VMM (e.g. KVM) can virtualize the MSRs. > > There are three classes of MSRs virtualization. > - non-configurable: TDX module directly virtualizes it. VMM can't > configure. the value set by KVM_SET_MSR_INDEX_LIST is ignored. > - configurable: TDX module directly virtualizes it. VMM can configure at > the VM creation time. The value set by KVM_SET_MSR_INDEX_LIST is used. > - #VE case > Guest TD would issue TDG.VP.VMCALL and > VMM handles the MSR hypercall. The value set by KVM_SET_MSR_INDEX_LIST > is used. > > Signed-off-by: Isaku Yamahata > Reviewed-by: Paolo Bonzini > --- [...] > + > +bool tdx_has_emulated_msr(u32 index, bool write) > +{ > + switch (index) { > + case MSR_IA32_UCODE_REV: > + case MSR_IA32_ARCH_CAPABILITIES: > + case MSR_IA32_POWER_CTL: > + case MSR_IA32_CR_PAT: > + case MSR_IA32_TSC_DEADLINE: > + case MSR_IA32_MISC_ENABLE: > + case MSR_PLATFORM_INFO: > + case MSR_MISC_FEATURES_ENABLES: > + case MSR_IA32_MCG_CAP: > + case MSR_IA32_MCG_STATUS: It not about this patch directly. Intel SDM says: "An attempt to write to IA32_MCG_STATUS with any value other than 0 would result in #GP". But in set_msr_mce(), IA32_MCG_STATUS is set without any check. Should it be checked against 0 if it is not host_initiated?