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18 Apr 2024 20:45:31 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson , Mingwei Zhang Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v4 00/17] pmu test bugs fix and improvements Date: Fri, 19 Apr 2024 11:52:16 +0800 Message-Id: <20240419035233.3837621-1-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Changes: v3 -> v4: * Fix the new found issue that pmu_counter_t.config crosses cache lines (patch 04) * Fix the cycles event false positive by introducing a warm-up phase instead of switching cycles events order in v3 (patch 07) * Use macro to replace hard-coded events index (Mingwei)(patches 08~10) * Simply the asm code to enable/disable GLOBAL_CTRL MSR in whole asm blob (patch 11) * Handle legacy CPUs without clflush/clflushopt/IBPB support (patches 14, 16) * Optimize emulated instruction validation (patch 17) All changes pass validation on Intel Sapphire Rapids and Emerald Rapids platforms against latest kvm-x86/next code (2d181d84af38). No tests on AMD platforms since no AMD platform on hand. Any tests on AMD platform are appreciated. History: v3: https://lore.kernel.org/lkml/20240103031409.2504051-1-dapeng1.mi@linux.intel.com/ v2: https://lore.kernel.org/lkml/20231031092921.2885109-1-dapeng1.mi@linux.intel.com/ v1: https://lore.kernel.org/lkml/20231024075748.1675382-1-dapeng1.mi@linux.intel.com/ Dapeng Mi (16): x86: pmu: Remove blank line and redundant space x86: pmu: Refine fixed_events[] names x86: pmu: Fix the issue that pmu_counter_t.config crosses cache line x86: pmu: Enlarge cnt[] length to 48 in check_counters_many() x86: pmu: Add asserts to warn inconsistent fixed events and counters x86: pmu: Fix cycles event validation failure x86: pmu: Use macro to replace hard-coded branches event index x86: pmu: Use macro to replace hard-coded ref-cycles event index x86: pmu: Use macro to replace hard-coded instructions event index x86: pmu: Enable and disable PMCs in loop() asm blob x86: pmu: Improve instruction and branches events verification x86: pmu: Improve LLC misses event verification x86: pmu: Adjust lower boundary of llc-misses event to 0 for legacy CPUs x86: pmu: Add IBPB indirect jump asm blob x86: pmu: Adjust lower boundary of branch-misses event x86: pmu: Optimize emulated instruction validation Xiong Zhang (1): x86: pmu: Remove duplicate code in pmu_init() lib/x86/pmu.c | 5 - x86/pmu.c | 386 ++++++++++++++++++++++++++++++++++++++++---------- 2 files changed, 308 insertions(+), 83 deletions(-) base-commit: e96011b32944b1ecca5967674ae243067588d1e7 -- 2.34.1