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Fri, 19 Apr 2024 02:38:53 -0700 (PDT) Date: Fri, 19 Apr 2024 15:08:47 +0530 From: Manivannan Sadhasivam To: Bjorn Helgaas Cc: Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I , Thierry Reding , Jonathan Hunter , Jingoo Han , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev, linux-tegra@vger.kernel.org, Niklas Cassel , Damien Le Moal Subject: Re: [PATCH v3 3/9] PCI: endpoint: Rename BME to Bus Master Enable Message-ID: <20240419093847.GB3636@thinkpad> References: <20240418-pci-epf-rework-v3-3-222a5d1ed2e5@linaro.org> <20240418161209.GA239309@bhelgaas> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240418161209.GA239309@bhelgaas> On Thu, Apr 18, 2024 at 11:12:09AM -0500, Bjorn Helgaas wrote: > On Thu, Apr 18, 2024 at 05:28:31PM +0530, Manivannan Sadhasivam wrote: > > BME which stands for 'Bus Master Enable' is not defined in the PCIe base > > spec even though it is commonly referred in many places (vendor docs). But > > to align with the spec, let's rename it to its expansion 'Bus Master > > Enable'. > > Thanks for doing this. I'm always in favor of using terms from the > spec. > > > - dev_dbg(dev, "Received BME event. Link is enabled!\n"); > > + dev_dbg(dev, "Received Bus Master Enable event. Link is enabled!\n"); > > Nothing to do with *this* patch, but this message reads a little weird > to me because setting Bus Master Enable has nothing to do with link > enablement. > That's my bad. I'll remove it. > Also incidental: some of these messages and comments refer to a "Bus > Master Enable *event*". Does "event" here refer to the act of the > host setting the Bus Master Enable bit in the Command register? This > is in qcom_pcie_ep_global_irq_thread(), so I assume there's something > in the endpoint hardware that generates an IRQ when the Command > register is written? > Yes, the PCIe endpoint controller generates an IRQ when host sets Bus Master Enable bit. > > - * pci_epc_bme_notify() - Notify the EPF device that the EPC device has received > > - * the BME event from the Root complex > > - * @epc: the EPC device that received the BME event > > + * pci_epc_bus_master_enable_notify() - Notify the EPF device that the EPC > > + * device has received the Bus Master > > + * Enable event from the Root complex > > + * @epc: the EPC device that received the Bus Master Enable event > > * > > * Invoke to Notify the EPF device that the EPC device has received the Bus > > - * Master Enable (BME) event from the Root complex > > + * Master Enable event from the Root complex > > There's no "set Bus Master Enable" transaction that would appear on > the PCIe link, so I assume "the Bus Master Enable event from the Root > Complex" is a way of saying something like "host has written the > Command register to set the Bus Master Enable bit"? > Yes. But looking at it again, it could be reworded as below: 'Invoke to notify the EPF device that the EPC device has generated the Bus Master Enable event due to host setting the Bus Master Enable bit in the Command register.' - Mani -- மணிவண்ணன் சதாசிவம்