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Date: Fri, 19 Apr 2024 13:40:33 +0200
Message-Id: <D0O2KG09X87O.1UR0G6BXCEJ5E@gmail.com>
Cc: <mochs@nvidia.com>, <csoto@nvidia.com>, <jamien@nvidia.com>,
 <smangipudi@nvidia.com>
Subject: Re: [PATCH] gpio: tegra186: Fix tegra186_gpio_is_accessible() check
From: "Thierry Reding" <thierry.reding@gmail.com>
To: "Prathamesh Shete" <pshete@nvidia.com>, <linus.walleij@linaro.org>,
 <brgl@bgdev.pl>, <jonathanh@nvidia.com>, <treding@nvidia.com>,
 <linux-gpio@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
 <linux-kernel@vger.kernel.org>
References: <20240416123501.12916-1-pshete@nvidia.com>
In-Reply-To: <20240416123501.12916-1-pshete@nvidia.com>

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On Tue Apr 16, 2024 at 2:35 PM CEST, Prathamesh Shete wrote:
> The controller has several register bits describing access control
> information for a given GPIO pin. When SCR_SEC_[R|W]EN is unset, it
> means we have full read/write access to all the registers for given GPIO
> pin. When SCR_SEC[R|W]EN is set, it means we need to further check the
> accompanying SCR_SEC_G1[R|W] bit to determine read/write access to all
> the registers for given GPIO pin.
>
> This check was previously declaring that a GPIO pin was accessible
> only if either of the following conditions were met:
>
>   - SCR_SEC_REN + SCR_SEC_WEN both set
>
>     or
>
>   - SCR_SEC_REN + SCR_SEC_WEN both set and
>     SCR_SEC_G1R + SCR_SEC_G1W both set
>
> Update the check to properly handle cases where only one of
> SCR_SEC_REN or SCR_SEC_WEN is set.
>
> Fixes: b2b56a163230 ("gpio: tegra186: Check GPIO pin permission before ac=
cess.")
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
> ---
>  drivers/gpio/gpio-tegra186.c | 22 ++++++++++++++--------
>  1 file changed, 14 insertions(+), 8 deletions(-)

Acked-by: Thierry Reding <treding@nvidia.com>

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