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Fri, 19 Apr 2024 14:28:21 GMT Received: from [10.216.17.233] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 19 Apr 2024 07:28:13 -0700 Message-ID: <4a83afeb-8e82-4f95-b44e-74d39d55f448@quicinc.com> Date: Fri, 19 Apr 2024 19:58:08 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/7] ipq9574: Enable PCI-Express support To: Alexandru Gagniuc , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Michael Turquette , Stephen Boyd , Manivannan Sadhasivam , , , , , , References: <20240415182052.374494-1-mr.nuke.me@gmail.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <20240415182052.374494-1-mr.nuke.me@gmail.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: f5HZFmDXBrCPKCpPNSOydsESSpTxuWBO X-Proofpoint-ORIG-GUID: f5HZFmDXBrCPKCpPNSOydsESSpTxuWBO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-19_09,2024-04-19_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 priorityscore=1501 bulkscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404190108 On 4/15/2024 11:50 PM, Alexandru Gagniuc wrote: > There are four PCIe ports on IPQ9574, pcie0 thru pcie3. This series > addresses pcie2, which is a gen3x2 port. The board I have only uses > pcie2, and that's the only one enabled in this series. > > I believe this makes sense as a monolithic series, as the individual > pieces are not that useful by themselves. > > In v2, I've had some issues regarding the dt schema checks. For > transparency, I used the following test invocations to test v3: > > make dt_binding_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml > make dtbs_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml > > Alexandru, Thanks for your contributions to the Qualcomm IPQ chipsets. I would like to inform you that we have also submitted the patches to enable the PCIe support on IPQ9574[1][2] and waiting for the ICC support[3] to land to enable the NOC clocks. [1] https://lore.kernel.org/linux-arm-msm/20230519090219.15925-1-quic_devipriy@quicinc.com/ [2] https://lore.kernel.org/linux-arm-msm/20230519085723.15601-1-quic_devipriy@quicinc.com/ [3] https://lore.kernel.org/linux-arm-msm/20240418092305.2337429-1-quic_varada@quicinc.com/ Please take a look at these patches as well. Thanks, Kathiravan T. > Changes since v2: > - reworked resets in qcom,pcie.yaml to resolve dt schema errors > - constrained "reg" in qcom,pcie.yaml > - reworked min/max intems in qcom,ipq8074-qmp-pcie-phy.yaml > - dropped msi-parent for pcie node, as it is handled by "msi" IRQ > > Changes since v1: > - updated new tables in phy-qcom-qmp-pcie.c to use lowercase hex numbers > - reorganized qcom,ipq8074-qmp-pcie-phy.yaml to use a single list of clocks > - reorganized qcom,pcie.yaml to include clocks+resets per compatible > - Renamed "pcie2_qmp_phy" label to "pcie2_phy" > - moved "ranges" property of pcie@20000000 higher up > > Alexandru Gagniuc (7): > dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 > clk: qcom: gcc-ipq9574: Add PCIe pipe clocks > dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller > PCI: qcom: Add support for IPQ9574 > dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY > phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY > arm64: dts: qcom: ipq9574: add PCIe2 nodes > > .../devicetree/bindings/pci/qcom,pcie.yaml | 35 +++++ > .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 36 ++++- > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 93 +++++++++++- > drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++ > drivers/pci/controller/dwc/pcie-qcom.c | 13 +- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++- > .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++ > include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 + > 8 files changed, 400 insertions(+), 7 deletions(-) >