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Cc: Krzysztof Kozlowski , Conor Dooley , Konstantin Pugin , Vladimir Zapolskiy , Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hugo Villeneuve , Lech Perczak , Ilpo =?iso-8859-1?Q?J=E4rvinen?= , Thomas Gleixner , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v4 2/3] dt-bindings: sc16is7xx: Add compatible line for XR20M1172 UART Message-ID: References: <20240419124506.1531035-1-rilian.la.te@ya.ru> <20240419124506.1531035-3-rilian.la.te@ya.ru> <20240419-glue-pyramid-584728c0076a@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo On Fri, Apr 19, 2024 at 05:34:44PM +0300, Konstantin P. wrote: > On Fri, Apr 19, 2024 at 5:24 PM Krzysztof Kozlowski wrote: > > On 19/04/2024 16:17, Konstantin P. wrote: .. > > Commits must stand on their own. Cover letter is not merged. This is the > > place where you add new hardware, so here you describe and explain the > > hardware. > > It is also described in patch 3 in the series. I need to repeat this > description in patch 2 too? > > Cite from patch 3: > > XR20M1172 register set is mostly compatible with SC16IS762, but it has > a support for additional division rates of UART with special DLD register. The point is, if I got it correctly, to have a few words in the description of the DT binding itself, so whoever reads the bindings (w/o even accessing the Git history of the project) may understand this. -- With Best Regards, Andy Shevchenko