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References: <20240419141249.609534-1-mwalle@kernel.org> <20240419141249.609534-2-mwalle@kernel.org>
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From: Ricardo Ribalda Delgado <ribalda@kernel.org>
Date: Fri, 19 Apr 2024 17:16:05 +0200
Message-ID: <CAPybu_0j-b7v0C-9-1D2Uzb5oo+2MR+KcqOn8uWBE0RQyaGbYg@mail.gmail.com>
Subject: Re: [PATCH v2 1/6] mtd: spi-nor: Remove support for Xilinx S3AN flashes
To: Michael Walle <mwalle@kernel.org>
Cc: Tudor Ambarus <tudor.ambarus@linaro.org>, Pratyush Yadav <pratyush@kernel.org>, 
	Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, 
	Vignesh Raghavendra <vigneshr@ti.com>, linux-kernel@vger.kernel.org, 
	linux-mtd@lists.infradead.org, Marek Vasut <marex@denx.de>, 
	Alexandre Desnoyers <alex@qtec.com>
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Hi Michael

Thanks for the cleanup. I have pinged my previous employer and they do
not have any product in production using S3AN.
So no blockers from my side.

[ccing Marek In case he knows about other users]

Regards

On Fri, Apr 19, 2024 at 4:14=E2=80=AFPM Michael Walle <mwalle@kernel.org> w=
rote:
>
> These flashes are kind of an oddball for the very old Xilinx Spartan 3
> FPGAs to store their bitstream. More importantly, they reuse the Atmel
> JEDEC manufacturer ID and in fact the at45db081d already blocks the use
> of the 3S700AN flash chip. It's time to sunset support for these
> flashes.
>
> Signed-off-by: Michael Walle <mwalle@kernel.org>
> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
> Cc: Ricardo Ribalda <ribalda@kernel.org>
Acked-by: Ricardo Ribalda <ribalda@chromium.org>
> ---
>  drivers/mtd/spi-nor/Makefile |   1 -
>  drivers/mtd/spi-nor/core.c   |   1 -
>  drivers/mtd/spi-nor/core.h   |   1 -
>  drivers/mtd/spi-nor/xilinx.c | 169 -----------------------------------
>  4 files changed, 172 deletions(-)
>  delete mode 100644 drivers/mtd/spi-nor/xilinx.c
>
> diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
> index 5e68468b72fc..5dd9c35f6b6f 100644
> --- a/drivers/mtd/spi-nor/Makefile
> +++ b/drivers/mtd/spi-nor/Makefile
> @@ -13,7 +13,6 @@ spi-nor-objs                  +=3D micron-st.o
>  spi-nor-objs                   +=3D spansion.o
>  spi-nor-objs                   +=3D sst.o
>  spi-nor-objs                   +=3D winbond.o
> -spi-nor-objs                   +=3D xilinx.o
>  spi-nor-objs                   +=3D xmc.o
>  spi-nor-$(CONFIG_DEBUG_FS)     +=3D debugfs.o
>  obj-$(CONFIG_MTD_SPI_NOR)      +=3D spi-nor.o
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 3e1f1913536b..cbe5f92eb0af 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -1986,7 +1986,6 @@ static const struct spi_nor_manufacturer *manufactu=
rers[] =3D {
>         &spi_nor_spansion,
>         &spi_nor_sst,
>         &spi_nor_winbond,
> -       &spi_nor_xilinx,
>         &spi_nor_xmc,
>  };
>
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 442786685515..072c69b0d06c 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -603,7 +603,6 @@ extern const struct spi_nor_manufacturer spi_nor_st;
>  extern const struct spi_nor_manufacturer spi_nor_spansion;
>  extern const struct spi_nor_manufacturer spi_nor_sst;
>  extern const struct spi_nor_manufacturer spi_nor_winbond;
> -extern const struct spi_nor_manufacturer spi_nor_xilinx;
>  extern const struct spi_nor_manufacturer spi_nor_xmc;
>
>  extern const struct attribute_group *spi_nor_sysfs_groups[];
> diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c
> deleted file mode 100644
> index f99118c691b0..000000000000
> --- a/drivers/mtd/spi-nor/xilinx.c
> +++ /dev/null
> @@ -1,169 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * Copyright (C) 2005, Intec Automation Inc.
> - * Copyright (C) 2014, Freescale Semiconductor, Inc.
> - */
> -
> -#include <linux/mtd/spi-nor.h>
> -
> -#include "core.h"
> -
> -#define XILINX_OP_SE           0x50    /* Sector erase */
> -#define XILINX_OP_PP           0x82    /* Page program */
> -#define XILINX_OP_RDSR         0xd7    /* Read status register */
> -
> -#define XSR_PAGESIZE           BIT(0)  /* Page size in Po2 or Linear */
> -#define XSR_RDY                        BIT(7)  /* Ready */
> -
> -#define XILINX_RDSR_OP(buf)                                            \
> -       SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0),                   \
> -                  SPI_MEM_OP_NO_ADDR,                                  \
> -                  SPI_MEM_OP_NO_DUMMY,                                 \
> -                  SPI_MEM_OP_DATA_IN(1, buf, 0))
> -
> -#define S3AN_FLASH(_id, _name, _n_sectors, _page_size)         \
> -       .id =3D _id,                                              \
> -       .name =3D _name,                                          \
> -       .size =3D 8 * (_page_size) * (_n_sectors),                \
> -       .sector_size =3D (8 * (_page_size)),                      \
> -       .page_size =3D (_page_size),                              \
> -       .flags =3D SPI_NOR_NO_FR
> -
> -/* Xilinx S3AN share MFR with Atmel SPI NOR */
> -static const struct flash_info xilinx_nor_parts[] =3D {
> -       /* Xilinx S3AN Internal Flash */
> -       { S3AN_FLASH(SNOR_ID(0x1f, 0x22, 0x00), "3S50AN", 64, 264) },
> -       { S3AN_FLASH(SNOR_ID(0x1f, 0x24, 0x00), "3S200AN", 256, 264) },
> -       { S3AN_FLASH(SNOR_ID(0x1f, 0x24, 0x00), "3S400AN", 256, 264) },
> -       { S3AN_FLASH(SNOR_ID(0x1f, 0x25, 0x00), "3S700AN", 512, 264) },
> -       { S3AN_FLASH(SNOR_ID(0x1f, 0x26, 0x00), "3S1400AN", 512, 528) },
> -};
> -
> -/*
> - * This code converts an address to the Default Address Mode, that has n=
on
> - * power of two page sizes. We must support this mode because it is the =
default
> - * mode supported by Xilinx tools, it can access the whole flash area an=
d
> - * changing over to the Power-of-two mode is irreversible and corrupts t=
he
> - * original data.
> - * Addr can safely be unsigned int, the biggest S3AN device is smaller t=
han
> - * 4 MiB.
> - */
> -static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr)
> -{
> -       u32 page_size =3D nor->params->page_size;
> -       u32 offset, page;
> -
> -       offset =3D addr % page_size;
> -       page =3D addr / page_size;
> -       page <<=3D (page_size > 512) ? 10 : 9;
> -
> -       return page | offset;
> -}
> -
> -/**
> - * xilinx_nor_read_sr() - Read the Status Register on S3AN flashes.
> - * @nor:       pointer to 'struct spi_nor'.
> - * @sr:                pointer to a DMA-able buffer where the value of t=
he
> - *              Status Register will be written.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr)
> -{
> -       int ret;
> -
> -       if (nor->spimem) {
> -               struct spi_mem_op op =3D XILINX_RDSR_OP(sr);
> -
> -               spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> -
> -               ret =3D spi_mem_exec_op(nor->spimem, &op);
> -       } else {
> -               ret =3D spi_nor_controller_ops_read_reg(nor, XILINX_OP_RD=
SR, sr,
> -                                                     1);
> -       }
> -
> -       if (ret)
> -               dev_dbg(nor->dev, "error %d reading SR\n", ret);
> -
> -       return ret;
> -}
> -
> -/**
> - * xilinx_nor_sr_ready() - Query the Status Register of the S3AN flash t=
o see
> - * if the flash is ready for new commands.
> - * @nor:       pointer to 'struct spi_nor'.
> - *
> - * Return: 1 if ready, 0 if not ready, -errno on errors.
> - */
> -static int xilinx_nor_sr_ready(struct spi_nor *nor)
> -{
> -       int ret;
> -
> -       ret =3D xilinx_nor_read_sr(nor, nor->bouncebuf);
> -       if (ret)
> -               return ret;
> -
> -       return !!(nor->bouncebuf[0] & XSR_RDY);
> -}
> -
> -static int xilinx_nor_setup(struct spi_nor *nor,
> -                           const struct spi_nor_hwcaps *hwcaps)
> -{
> -       u32 page_size;
> -       int ret;
> -
> -       ret =3D xilinx_nor_read_sr(nor, nor->bouncebuf);
> -       if (ret)
> -               return ret;
> -
> -       nor->erase_opcode =3D XILINX_OP_SE;
> -       nor->program_opcode =3D XILINX_OP_PP;
> -       nor->read_opcode =3D SPINOR_OP_READ;
> -       nor->flags |=3D SNOR_F_NO_OP_CHIP_ERASE;
> -
> -       /*
> -        * This flashes have a page size of 264 or 528 bytes (known as
> -        * Default addressing mode). It can be changed to a more standard
> -        * Power of two mode where the page size is 256/512. This comes
> -        * with a price: there is 3% less of space, the data is corrupted
> -        * and the page size cannot be changed back to default addressing
> -        * mode.
> -        *
> -        * The current addressing mode can be read from the XRDSR registe=
r
> -        * and should not be changed, because is a destructive operation.
> -        */
> -       if (nor->bouncebuf[0] & XSR_PAGESIZE) {
> -               /* Flash in Power of 2 mode */
> -               page_size =3D (nor->params->page_size =3D=3D 264) ? 256 :=
 512;
> -               nor->params->page_size =3D page_size;
> -               nor->mtd.writebufsize =3D page_size;
> -               nor->params->size =3D nor->info->size;
> -               nor->mtd.erasesize =3D 8 * page_size;
> -       } else {
> -               /* Flash in Default addressing mode */
> -               nor->params->convert_addr =3D s3an_nor_convert_addr;
> -               nor->mtd.erasesize =3D nor->info->sector_size;
> -       }
> -
> -       return 0;
> -}
> -
> -static int xilinx_nor_late_init(struct spi_nor *nor)
> -{
> -       nor->params->setup =3D xilinx_nor_setup;
> -       nor->params->ready =3D xilinx_nor_sr_ready;
> -
> -       return 0;
> -}
> -
> -static const struct spi_nor_fixups xilinx_nor_fixups =3D {
> -       .late_init =3D xilinx_nor_late_init,
> -};
> -
> -const struct spi_nor_manufacturer spi_nor_xilinx =3D {
> -       .name =3D "xilinx",
> -       .parts =3D xilinx_nor_parts,
> -       .nparts =3D ARRAY_SIZE(xilinx_nor_parts),
> -       .fixups =3D &xilinx_nor_fixups,
> -};
> --
> 2.39.2
>