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From: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	cros-qcom-dts-watchers@chromium.org,
	Rob Herring <robh@kernel.org>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Neil Armstrong <neil.armstrong@linaro.org>
Subject: Re: (subset) [PATCH v2 00/21] Add PCIe bridge node in DT for Qcom SoCs
Date: Sun, 21 Apr 2024 17:29:19 -0500
Message-ID: <171373856771.1196479.2864036969713172935.b4-ty@kernel.org>
In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org>
References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org>
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On Thu, 21 Mar 2024 16:46:20 +0530, Manivannan Sadhasivam wrote:
> On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> for each controller instance. Hence, this series adds a DT node for the
> PCIe bridges across all SoCs.
> 
> There is no functionality change with this series, but the PCIe bridge
> representation in DT will be necessary to add the DT node for the client
> devices like the one proposed in power sequencing series [1].
> 
> [...]

Applied, thanks!

[17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node
        commit: 0c4d19b125401957123989a25094972cf0e77670
[18/21] ARM: dts: qcom: ipq4019: Add PCIe bridge node
        commit: ed9b196418d4e2fa4f6c27b61a92c2038e1ba04d
[19/21] ARM: dts: qcom: apq8064: Add PCIe bridge node
        commit: 27cb9eccf94cb163f9bf3b945f249ab7c42861db
[20/21] ARM: dts: qcom: sdx55: Add PCIe bridge node
        commit: 669841a2eff4c0132841dea3ae40d9148a36f257

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>