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Mon, 22 Apr 2024 01:21:07 +0000 From: Minda Chen To: Krishna Kurapati , Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Wesley Cheng , Konrad Dybcio , Greg Kroah-Hartman , Conor Dooley , Thinh Nguyen , Felipe Balbi , Johan Hovold CC: "devicetree@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "quic_ppratap@quicinc.com" , "quic_jackp@quicinc.com" Subject: Re: [PATCH v21 0/9] Add multiport support for DWC3 controllers Thread-Topic: [PATCH v21 0/9] Add multiport support for DWC3 controllers Thread-Index: AQHakt5cTCGj6o4U1kO+Ia5MuXnVybFzgPUA Date: Mon, 22 Apr 2024 01:21:07 +0000 Message-ID: References: <20240420044901.884098-1-quic_kriskura@quicinc.com> In-Reply-To: <20240420044901.884098-1-quic_kriskura@quicinc.com> Accept-Language: en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-Network-Message-Id: 636e2538-c519-4436-6794-08dc626a7c4d X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2024 01:21:07.1212 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 2rg02vXBpY1MTOBP0Bq//MWwKI6z+EYiq0wP9qYDKSVY814loPDHRUJr6Oa/sys0DnBoNbUA+ou1UMMOfQHvmaAVUiOz3KLRPI3uQayBDBs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0736 >=20 > Currently the DWC3 driver supports only single port controller which requ= ires at > most two PHYs ie HS and SS PHYs. There are SoCs that has > DWC3 controller with multiple ports that can operate in host mode. > Some of the port supports both SS+HS and other port supports only HS mode= . >=20 > This change primarily refactors the Phy logic in core driver to allow mul= tiport > support with Generic Phy's. >=20 > The DWC3 controller supports up to 15 High-Speed phys and 4 SuperSpeed ph= ys. > The multiport controller in Qualcomm SA8295P is paired with two High-Spee= d + > SuperSpeed and two High-Speed-only ports. It is assumed that the N > SuperSpeed PHYs are paired with the first N High-Speed PHYs. >=20 Hi All, Thinh Can DW multiple port host patches be (patch 1-4) accepted first? Other mul= tiport vendor will use this.