Received-SPF: pass (google.com: domain of linux-kernel+bounces-153307-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161;
Message-ID: <4619b7ec-3d04-47c9-bc43-75eac26b3f14@theobroma-systems.com>
Date: Mon, 22 Apr 2024 13:49:06 +0200
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v2] arm64: dts: rockchip: add PCIe3 support on
 rk3588-jaguar
To: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org,
 linux-kernel@vger.kernel.org, dsimic@manjaro.org,
 Heiko Stuebner <heiko.stuebner@cherry.de>
References: <20240418124445.2360491-1-heiko@sntech.de>
Content-Language: en-US
From: Quentin Schulz <quentin.schulz@theobroma-systems.com>
In-Reply-To: <20240418124445.2360491-1-heiko@sntech.de>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?utf-8?B?STM1QUg2TVN6eUdXRUtmMVNMbnRSTmllenRmd3N0YlZPT2kvbGNqM1E2cHAy?=
 =?utf-8?B?ZVE2OUVjYmt0UGY3RDV0Tit1b3MzR251a0RBZzkyQnpMNVRuazdrUVVCTWI4?=
 =?utf-8?B?UnBwMHYxL1FCSDlVa2JsZFJRU1RQdDNQaWVGM1JrU3U4blk1MGdTdHZCVDRh?=
 =?utf-8?B?ZlJQY2RUU0YrbFpEL3hheFd5QXUyNkpWUkc0enp3QitaUS9xMmNaODhiWUJC?=
 =?utf-8?B?UVhOTWlXdzQydTJ2cjhBaC9ZNWl4T3NHa0RkcGVJbS9QL3V4a3dQb2hlejhp?=
 =?utf-8?B?VVUybE5GZmNxZVltbGpsTWlrTXlNK2hWRGJaQ1JZZDJUOXEydWZTWEFGQU9G?=
 =?utf-8?B?dHdiRURkZ1d5S2hEaWcvMndxUGoreWwydnU0SS9BNHQ5RHVWTlJ3b3R6a1RC?=
 =?utf-8?B?cGxXbGlaMXJ6U05ZUUIrZHdTTW5iZkhGNU1qVFEzTTEvZTBPQVYrMm5uK1o0?=
 =?utf-8?B?ZUNvSDFRNVA1ay83WFRSLzlQVDkyS3g2VUQwcmdWdXJCVk10MEk4THRUTGti?=
 =?utf-8?B?WkIydU51blFlM1NkeEx4SHdFZGFHS084U0FMSHFoTWdkK3NvUDJiL0FiWlVt?=
 =?utf-8?B?dXV1VmN0MWErd3FMelFXSFVJS2VNWXhQaHNJS3BoVVVUKy9qQVNsZG1La25N?=
 =?utf-8?B?WlZRZ3BHdkhnSXVncXdNNXhJLzVLRE93YTd3dnFoSE1aRXJ2bmpWbWtFcTQ1?=
 =?utf-8?B?a29FcytUeHJaN0p5V0R1Y09lWVh1VWhPZHk5b2FObVZsWlU3YzhlR1NWWXgx?=
 =?utf-8?B?SjdNTHlQZWljRTRWaEErS3p4TXNGUkV0NUFmUUFxNVFGYTRZcE81R2FLT3Iz?=
 =?utf-8?B?d2lpVDd1VE9XSXB1bWZaSTMzcXR0TjlmUXlwaS92V0ZQaVRkVjZhdi9lemc1?=
 =?utf-8?B?SnRPbExkdGhTTFdFTVJuc00vWnFSaklqUHVZTzJoRlpWUDlBTkk5V0xqc2Y4?=
 =?utf-8?B?Tng5N2hsTXlsdGRYSzBPNEJ5TW9KZkE0bEluSTVrbmxLQmY2S3Yrazlka0I1?=
 =?utf-8?B?K09oc0NndmVIM1IzcWxaYmhQMzVRZ1Q4TjBNb1NlTnVST3JZL3F2Qmd1a2NS?=
 =?utf-8?B?dkw1WTRRN2NrOHRYQlNHdWhXSnJKN3RDT1BLcEh3MVpCdEU4RXdwSzhNREZi?=
 =?utf-8?B?UWRFWkwvazRNOHpwWEVNOFNveEpscXJXWUtYNGtvSlJFM0diemZaVnJTOElj?=
 =?utf-8?B?cjRnNHdPcHE5S2YyNEZuaFdlSllPWm5iOEdPRnlSWUhVYk1rTmJXSENSVDJH?=
 =?utf-8?B?UVkvTEVjM0o0c1BiV2NUSkhsRXROYUpnaFBsdkNGMzZTR0kxdGVkL09Jelpr?=
 =?utf-8?B?MGNud1dHM3NLRmlWbFVmUlU0akhqck1Yc21qU3ZJeGhaM2NFYjFjU245eEg3?=
 =?utf-8?B?ZlI2bW1CMmltaU02MEZBZnZVL0VSaDlHSU5KZUdXdTF5RUxOemtYYk1FeXpE?=
 =?utf-8?B?TmpVbmRNWTloVEVvbU80bVRhakZBVHg0eFp0akJHdmxIZ3p2ZmI0dUxCUHZN?=
 =?utf-8?B?dDk2VDZqNHhjVEdYK2FFNlhjMUExQTl3YVlCREV6cWszYkdnRjNObjhtRGYz?=
 =?utf-8?B?MmNWZlBIb0p5TE1yQ0hiR1AxRkxvSkgwa0QzVUVPcHpnQU9FeEdZQm1TWmtY?=
 =?utf-8?B?OWJyaFRSZ0c0eGdiMHRxc1FzbXpSVWxSbk9Jb1BueXdWSkdDU1NnMDd2bEd3?=
 =?utf-8?B?MTN2T1owaW9uTkdDT0ZxVnFRSHh5TUF1L0VuYWJ5YzR2UG9OTUtsYUlKUmU4?=
 =?utf-8?B?SUpQYmZvNWMzek9TSkF5d2ZLQ2FBMEgwSElMYndtd0hJOTJGVVBYVWJHY3V2?=
 =?utf-8?B?dGlBR1gzeUcwWC9vY1ZQSmFleUQzRGtkVEJQazNJVkU3REpZbFhnNVVLQnJo?=
 =?utf-8?B?SVNiWUg2aEhYN3FxaFFha0hiMWNOK1MrZnVjVTJESzVEVzBKaGpPK2JJK3h0?=
 =?utf-8?B?RU1yVG1STDF2RzBITjhRV1BRRkllbURDaG9LT3lBYStHTnZpOXlhWVRvcW9i?=
 =?utf-8?B?MXAvdUxKdWRvS0dhNzJUeHh3ajNXWmUxTU4zWlZLd1Y0N0VYQWliV0tDaTlO?=
 =?utf-8?B?RkU4QkpQMkJBeUVjTGhVT05DbEcxN3M4Tyt2b255TUhkTEtCakh0d05naFJX?=
 =?utf-8?B?VWtPUVpVaXVMd0xkZ0NndVdRN0JlZHpDZHV0QkM2MjBHM2dZaXcwS0hnR0o1?=
 =?utf-8?Q?kSAKEe8EP6eTu6iec2dq1xg=3D?=
X-OriginatorOrg: theobroma-systems.com
X-MS-Exchange-CrossTenant-Network-Message-Id: b24660a8-c806-4cc3-de51-08dc62c237f5
X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB4842.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2024 11:49:08.3448
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 5e0e1b52-21b5-4e7b-83bb-514ec460677e
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: OcwhjewwLNZXLoaLkKnt7KETC9PPklvYDJASk00UO/8ovZlFRJ7+zHnZxanxyrDD35fbO/cezWysNfeUoHDQqOBPuWBvbXXooPt0gwN/fba3ZqZLG5hyp3nXQ5YAs/Rf
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA2PR04MB10123

Hi Heiko,

On 4/18/24 14:44, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@cherry.de>
> 
> The Jaguar SBC provides an M.2 slot connected to the pcie3 controller.
> In contrast to a number of other boards the pcie-refclk is gpio-controlled,
> so the necessary clock and is added to the list of pcie3 clocks.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
> ---
> changes in v2:
> - "an" M.2 slot (Dragan)
> - pinctrl for refclk-en and reset pin (Quentin)
> - don't repurpose the pcie30x4_pins pinctrl entry for only wake (Quentin)
> 
>   .../arm64/boot/dts/rockchip/rk3588-jaguar.dts | 64 +++++++++++++++++++
>   1 file changed, 64 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
> index 4076c92668ba..3407e777e97b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
> @@ -72,6 +72,27 @@ led-1 {
>   		};
>   	};
>   
> +	/*
> +	 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
> +	 * clock generator.
> +	 * The clock output is gated via the OE pin on the clock generator.
> +	 * This is modeled as a fixed-clock plus a gpio-gate-clock.
> +	 */
> +	pcie_refclk_gen: pcie-refclk-gen-clock {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <1000000000>;
> +	};
> +
> +	pcie_refclk: pcie-refclk-clock {
> +		compatible = "gpio-gate-clock";
> +		clocks = <&pcie_refclk_gen>;
> +		#clock-cells = <0>;
> +		enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pcie30x4_clkreqn_m0>;
> +	};
> +
>   	pps {
>   		compatible = "pps-gpio";
>   		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
> @@ -358,6 +379,30 @@ &pcie2x1l0 {
>   	status = "okay";
>   };
>   
> +&pcie30phy {
> +	status = "okay";
> +};
> +
> +&pcie3x4 {
> +	/*
> +	 * The board has a gpio-controlled "pcie_refclk" generator,
> +	 * so add it to the list of clocks.
> +	 */
> +	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
> +		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
> +		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
> +		 <&pcie_refclk>;
> +	clock-names = "aclk_mst", "aclk_slv",
> +		      "aclk_dbi", "pclk",
> +		      "aux", "pipe",
> +		      "ref";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>;
> +	reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */
> +	vpcie3v3-supply = <&vcc3v3_mdot2>;
> +	status = "okay";
> +};
> +
>   &pinctrl {
>   	emmc {
>   		emmc_reset: emmc-reset {
> @@ -376,6 +421,25 @@ led1_pin: led1-pin {
>   			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
>   		};
>   	};
> +
> +	pcie30x4 {
> +		pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 {
> +			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
> +		pcie30x4_perstn_m0: pcie30x4-perstn-m0 {
> +			rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
> +		pcie30x4_waken_m0: pcie30x4-waken-m0 {
> +			/*
> +			 * pcie30x4_clkreqn_m0 is used by the refclk generator
> +			 * pcie30x4_perstn_m0 is used as via the reset-gpio

s/used as/used as GPIO/ ?

But also, I think we don't need these comments anymore as we are not 
reusing an existing node so there's no real reason to give for only 
having pcie30x4_waken_m0 muxed in a node called pcie30x4_waken_m0 :)

Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>

Thanks,
Quentin