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Mon, 22 Apr 2024 12:06:10 GMT Received: from [10.253.39.160] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 22 Apr 2024 05:06:08 -0700 Message-ID: Date: Mon, 22 Apr 2024 20:06:06 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] bus: mhi: host: pci_generic: Add edl callback to enter EDL To: Manivannan Sadhasivam CC: Mayank Rana , , , , , References: <1713170945-44640-1-git-send-email-quic_qianyu@quicinc.com> <1713170945-44640-4-git-send-email-quic_qianyu@quicinc.com> <17d94b91-137c-409c-8af3-f32f1af2eb71@quicinc.com> <4b684db2-d384-404a-9c54-60d79ac7cf9f@quicinc.com> <20240422080837.GC9775@thinkpad> Content-Language: en-US From: Qiang Yu In-Reply-To: <20240422080837.GC9775@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GTsngNAd7myf_oDO4773FwzjWvB_ZHt3 X-Proofpoint-ORIG-GUID: GTsngNAd7myf_oDO4773FwzjWvB_ZHt3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-22_09,2024-04-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 suspectscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 spamscore=0 phishscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404220054 On 4/22/2024 4:08 PM, Manivannan Sadhasivam wrote: > On Wed, Apr 17, 2024 at 12:41:25PM +0800, Qiang Yu wrote: > > [...] > >>>>>>> +    ret = mhi_get_channel_doorbell(mhi_cntrl, &val); >>>>>>> +    if (ret) >>>>>>> +        return ret; >>>>>> Don't we need error handling part here i.e. calling >>>>>> mhi_cntrl->runtime_put() as well mhi_device_put() ? >>>>> Hi Mayank >>>>> >>>>> After soc_reset, device will reboot to EDL mode and MHI state >>>>> will be SYSERR. So host will fail to suspend >>>>> anyway. The "error handling" we need here is actually to enter >>>>> EDL mode, this will be done by SYSERR irq. >>>>> Here, mhi_cntrl->runtime_put() and mhi_device_put() are only to >>>>> balance mhi_cntrl->runtime_get() and >>>>> mhi_device_get_sync(). >>>>> >>>>> Thanks, >>>>> Qiang >>>> I am saying is there possibility that mhi_get_channel_doorbell() >>>> returns error ? >>>> If yes, then why don't we need error handling as part of it. you are >>>> exiting if this API return error without doing anything. >>> I think here mhi_get_channel_doorbell will not return error. But I still >>> add a error checking because it invoked mhi_read_reg, which is a must >>> check >>> API. For modem mhi controller, this API eventually does a memory read. >>> This memory read will return a normal value if link is up and all f's if >>> link >>> is bad. >>> >>> Thanks, >>> Qiang >> Actually, mhi_get_channel_doorbell should also be used in mhi_init_mmio to >> replace the getting chdb operation by invoking mhi_read_reg as Mani >> commented. >> In mhi_init_mmio, we invoke mhi_read_reg many times, but there is also not >> additionnal error handling. >> >> I'm not very sure the reason but perhaps if mhi_read_reg returns error (I >> don't >> know which controller will provide a memory read callback returning errors), > Take a look at AIC100 driver: drivers/accel/qaic/mhi_controller.c > >> most >> probably something is wrong in PCIe, which is not predictable by MHI and we >> can >> not add err handling every time invoking mhi_read_reg. But we have a timer >> to >> do health_check in pci_generic.c. If link is down, we will do >> pci_function_reset >> to try to reovery. >> > Right, but the MHI stack is designed to be bus agnostic. So if we happen to use > it with other busses like USB, I2C etc... then read APIs may fail. > > Even with PCIe, read transaction may return all 1 response and MHI needs to > treat it as an error condition. But sadly, both pci_generic and ath controllers > are not checking for invalid read value. But those need to be fixed. > > Regarding Mayank's query, you should do error cleanups if > mhi_get_channel_doorbell() API fails. > > - Mani Hi Mani, Mayank Checked drivers/accel/qaic/mhi_controller.c, the mhi_read_reg callback of AIC100 does return -EIO if it reads out all'f. Considering that pci_generic controller also needs to check for invalid read value which is not fixed though. It's better to invoke mhi_cntrl->runtime_put() and mhi_device_put() as error cleanups if mhi_get_channel_doorbell returns error here. Let me address all your comments and prepare next version patch. Thanks, Qiang >