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Hartmann" In-Reply-To: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> References: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> Subject: Re: (subset) [PATCH v12 0/7] drm/meson: add support for MIPI DSI Display Message-Id: <171380506905.4152979.12753297685732463141.b4-ty@linaro.org> Date: Mon, 22 Apr 2024 18:57:49 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.12.4 Hi, On Wed, 03 Apr 2024 09:46:31 +0200, Neil Armstrong wrote: > The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), > with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI > glue on the same Amlogic SoCs. > > This is a follow-up of v5 now the DRM patches are applied, the clk & DT changes > remains for a full DSI support on G12A & SM1 platforms. > > [...] Thanks, Applied to https://gitlab.freedesktop.org/drm/misc/kernel.git (drm-misc-next) [4/7] drm/meson: gate px_clk when setting rate https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/5c9837374ecf55a1fa3b7622d365a0456960270f -- Neil