Received-SPF: pass (google.com: domain of linux-kernel+bounces-153938-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223;
Message-ID: <17930444-3740-f874-91e7-3ed81304b1a9@amd.com>
Date: Mon, 22 Apr 2024 14:46:36 -0500
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101
 Thunderbird/102.15.1
Subject: Re: [PATCHv2] x86/tdx: Preserve shared bit on mprotect()
Content-Language: en-US
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
 tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com
Cc: sathyanarayanan.kuppuswamy@linux.intel.com, hpa@zytor.com,
 seanjc@google.com, elena.reshetova@intel.com, rick.p.edgecombe@intel.com,
 x86@kernel.org, linux-kernel@vger.kernel.org, Chris Oo <cho@microsoft.com>,
 Dexuan Cui <decui@microsoft.com>
References: <20240419201353.3937135-1-kirill.shutemov@linux.intel.com>
From: Tom Lendacky <thomas.lendacky@amd.com>
In-Reply-To: <20240419201353.3937135-1-kirill.shutemov@linux.intel.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?utf-8?B?cTh0b1NzYjBtWVBVMW5kNzdQeXJzMHpFdkcvV05OSGZaUmFZaW5lT0NlTC95?=
 =?utf-8?B?ZEwzZDI3ek9pUFUxQWtjcGF2a0ZrZXZGZmlQL3Q1MlROUEo5dXk1cGVEZ2dq?=
 =?utf-8?B?QlgrMGZ5ZU5pT3FPMXFCNGpoUWxoUHk2SWxFSFRORUNkQmY5UHFJSUdldEhx?=
 =?utf-8?B?bzFDL3ZLMVBQL2VzcEtFNHlUSEI3bXUwRHJDZDVUeUo5dEpjc1JKZzFRc29J?=
 =?utf-8?B?SWJmdk9rVkRGd3NDdFdRSmFLR3ZmZmVYVU9FY1JLdXVhQnV2emJ2UU14Wjhw?=
 =?utf-8?B?S2JSTWhBUlp3YXYzMXBDTXdTR0JzUGc4QVNYM2k3K3J0bndZcFZVM0hRRkFK?=
 =?utf-8?B?TWUwbUxoVnlCSkdpQ2NQaHpyMXY2bEpRQ1l2UWdDSW0wYVFtKzZDQWFIblJi?=
 =?utf-8?B?TkxOMnhNRmFDWHBOWVF4SmQ1S0czQzB5eC95RGdHdFBqVFpoY3UvS09HTWt3?=
 =?utf-8?B?aHFwOVQ4TDZlRUxtOHhIU0duNWpQcUdDS3dDZC81UXFMbHRacExtS1lrZ25w?=
 =?utf-8?B?TzNBejJmUzRNaWVrdXk0WHh2U0xEVWFmUXRVK0dOQU1ROHZ4d25sUVF2cXdu?=
 =?utf-8?B?ODJkVFh2RXFtc1JhbjJlUmdGdkpWQmF0d0w0WHYzaHR5NGMwQUYzakhkQW5h?=
 =?utf-8?B?Wnk5RHB1b3ZuSnoyRDVTbzhsT2w5bEpKVndaUmtRM2pBTGNuaEc1MVh2b2R5?=
 =?utf-8?B?dG5JZlJnK2VWL09TMVBTMnhFUTdsNUtZZzZqSkk1NlVwK3ZtZUx1eEJCMXVF?=
 =?utf-8?B?REpXNDdmM0Y1dENXaFhoOGltRWJQSlFHSWQxcW5KYkJWUXFQWVdLK2p0Z0JD?=
 =?utf-8?B?V1ZycnRnUGNrUWY5WEgxQ0U0YUpkeGdhZlM2Y2RXVzJVeWdpSjk1NFF2QzFy?=
 =?utf-8?B?MDBvaWtHdjVYUW9aUnNmUHlnWlQ0L1dvdVdnczRjOTdaL3FmbUxuQVhpVXVS?=
 =?utf-8?B?QlFNd1U0ZDdlMXJMRlFWSTFDM2ZqdkNlRWNjTGRpTHNuUlFJaVpyRkhrSXBB?=
 =?utf-8?B?QlBsTGwwTFpHU01VNlVlUXRzaXVVaFJLMHpPZkluelIvcFRTL0VIbUtHNDg2?=
 =?utf-8?B?Y0g2U1ZzMWhOU1RCVG1NNndjTi9QSmFjZ0NUanh2NldnU3hCYVBnd0JPMTY4?=
 =?utf-8?B?ME04allxeG01aW50U0JSQlJPOGhSL0x1aFkzQm53cFJ2SlV2V2dpSUYzN2c2?=
 =?utf-8?B?NUVGOXNxNzJwMGRmNVE3Q3RPRk5LdjdiQnRpSW1RRkF4TXFGeXdYSUtaZ0d1?=
 =?utf-8?B?YmUwMnpQVEdYMXZZM2wrWFRQYjZpNTdwVlFVeW5semNsdDZsZ3NvZ2sycVAv?=
 =?utf-8?B?ejBSOGcyc1QwZ2p6ZWp1akhyMVRHTlZiV0lodXNjNk5VQ1ExUW1nbzlyZENE?=
 =?utf-8?B?R28zOU1kTDFFS3RGRDJpaHFNc0U3c0UyUi9HUFRzYXhyZWdFSzhQNStZUWp2?=
 =?utf-8?B?Yk8wNHdKbG95b1g4QlVJOWtlSkNwdjJxeUZUUlA4M0V6UXNPQ2c1V2RWSUR3?=
 =?utf-8?B?Y3lqSmh0dm83WGgzb0ZReEJzbXNWZU9KV3pWTXMwZ2t0c1NKZldnZG0xT0tT?=
 =?utf-8?B?UDdQL1pqenJiYlJMeUdOM2xJd0tBMEVSUGhXSVF6bUNSWWQ4bjJDUHZrNEFT?=
 =?utf-8?B?TWlHdTFjK252WkNpTmhrb0dWWXpmV09HY2JkU29OTWpFZU4vNE9PWUtMaDQ1?=
 =?utf-8?B?em0xazU5cXVnZEVUOXBycm1idFZmSU1LTmdKR3lnZ1czanphOFg3MjNwZGo1?=
 =?utf-8?B?NTlOVEVhWVRCeGJxOUR6ZlhPenNIL0ozVEV2R3ozUDZFYTJUVG5BalRQNFRM?=
 =?utf-8?B?UHZTaVdTdC9kMjc0cEpUSGtXczl3RzdYN2tZVXdzckZxenJsenBZTUFkeW1G?=
 =?utf-8?B?KzFzWk12M21TaTBhWFA1bjk0RHJlV1Jpd3ZycStya2lGNnV1cnhWYXZIS1U5?=
 =?utf-8?B?Y3NUWkN6M2U3VS9JOEhoamYzUFRsd2FiMlpyakExbzJDR2h4UnpDb3dIY3Nn?=
 =?utf-8?B?YkJqWWVXbGoxQ3YwbXNPNmYrRklDWUNZam1QUTh4b1RtK2RYMDVQYzR1RzN2?=
 =?utf-8?B?MzE5dDVCaHBuQTNGODBZdmJiNENHVFFSbFAxUloxQW5YeUZYYTNSNWd0WFpi?=
 =?utf-8?Q?7YmlN4LfaDJT4oE6FGDdbLGyL?=
X-OriginatorOrg: amd.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 9cc13a9c-c12a-485e-a0d4-08dc6304ec9c
X-MS-Exchange-CrossTenant-AuthSource: BL1PR12MB5732.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2024 19:46:38.1745
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: WE85zcL3BJuz8Cb3ghRxJ3yDwzl6oRAHPde9K6DuIXonX0aB7Vrb52anB32OtxEYHzTRtwtbesyoq2z5R6h3sw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6874

On 4/19/24 15:13, Kirill A. Shutemov wrote:
> The TDX guest platform takes one bit from the physical address to
> indicate if the page is shared (accessible by VMM). This bit is not part
> of the physical_mask and is not preserved during mprotect(). As a
> result, the 'shared' bit is lost during mprotect() on shared mappings.
> 
> _COMMON_PAGE_CHG_MASK specifies which PTE bits need to be preserved
> during modification. AMD includes 'sme_me_mask' in the define to
> preserve the 'encrypt' bit.
> 
> To cover both Intel and AMD cases, include 'cc_mask' in
> _COMMON_PAGE_CHG_MASK instead of 'sme_me_mask'.
> 
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> Fixes: 41394e33f3a0 ("x86/tdx: Extend the confidential computing API to support TDX guests")
> Reported-and-tested-by: Chris Oo <cho@microsoft.com>
> Reviewed-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Cc: Tom Lendacky <thomas.lendacky@amd.com>

Appears to be no functional change on the AMD side.

Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>

> Cc: Dexuan Cui <decui@microsoft.com>
> ---
> 
>   v2:
>     - Fix build for !CONFIG_ARCH_HAS_CC_PLATFORM
> 
> ---
>   arch/x86/include/asm/coco.h          | 1 +
>   arch/x86/include/asm/pgtable_types.h | 3 ++-
>   2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/include/asm/coco.h b/arch/x86/include/asm/coco.h
> index c086699b0d0c..ac8cd4447d48 100644
> --- a/arch/x86/include/asm/coco.h
> +++ b/arch/x86/include/asm/coco.h
> @@ -25,6 +25,7 @@ u64 cc_mkdec(u64 val);
>   void cc_random_init(void);
>   #else
>   #define cc_vendor (CC_VENDOR_NONE)
> +#define cc_mask 0
>   
>   static inline u64 cc_mkenc(u64 val)
>   {
> diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
> index 8857d811fb5d..2f321137736c 100644
> --- a/arch/x86/include/asm/pgtable_types.h
> +++ b/arch/x86/include/asm/pgtable_types.h
> @@ -148,7 +148,7 @@
>   #define _COMMON_PAGE_CHG_MASK	(PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT |	\
>   				 _PAGE_SPECIAL | _PAGE_ACCESSED |	\
>   				 _PAGE_DIRTY_BITS | _PAGE_SOFT_DIRTY |	\
> -				 _PAGE_DEVMAP | _PAGE_ENC | _PAGE_UFFD_WP)
> +				 _PAGE_DEVMAP | _PAGE_CC | _PAGE_UFFD_WP)
>   #define _PAGE_CHG_MASK	(_COMMON_PAGE_CHG_MASK | _PAGE_PAT)
>   #define _HPAGE_CHG_MASK (_COMMON_PAGE_CHG_MASK | _PAGE_PSE | _PAGE_PAT_LARGE)
>   
> @@ -173,6 +173,7 @@ enum page_cache_mode {
>   };
>   #endif
>   
> +#define _PAGE_CC		(_AT(pteval_t, cc_mask))
>   #define _PAGE_ENC		(_AT(pteval_t, sme_me_mask))
>   
>   #define _PAGE_CACHE_MASK	(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)