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From: Sean Anderson <sean.anderson@linux.dev>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>,
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	Michal Simek <michal.simek@amd.com>,
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	Sean Anderson <sean.anderson@linux.dev>,
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	Bharat Kumar Gogada <bharatku@xilinx.com>,
	Conor Dooley <conor+dt@kernel.org>,
	Hyun Kwon <hyun.kwon@xilinx.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Michal Simek <michal.simek@xilinx.com>,
	devicetree@vger.kernel.org
Subject: [PATCH 0/7] PCI: xilinx-nwl: Add phy support
Date: Mon, 22 Apr 2024 15:58:57 -0400
Message-Id: <20240422195904.3591683-1-sean.anderson@linux.dev>
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Add phy subsystem support for the xilinx-nwl PCIe controller. This
series also includes several small fixes and improvements.


Sean Anderson (7):
  dt-bindings: pci: xilinx-nwl: Add phys
  PCI: xilinx-nwl: Fix off-by-one
  PCI: xilinx-nwl: Fix register misspelling
  PCI: xilinx-nwl: Rate-limit misc interrupt messages
  PCI: xilinx-nwl: Clean up clock on probe failure/removal
  PCI: xilinx-nwl: Add phy support
  [RFT] arm64: zynqmp: Add PCIe phys

 .../bindings/pci/xlnx,nwl-pcie.yaml           |   8 ++
 .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    |   2 +
 drivers/pci/controller/pcie-xilinx-nwl.c      | 124 ++++++++++++++----
 3 files changed, 111 insertions(+), 23 deletions(-)

-- 
2.35.1.1320.gc452695387.dirty