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Date: Tue, 23 Apr 2024 10:10:14 +0530
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Reply-To: nikunj@amd.com
Subject: Re: [PATCH v8 09/16] x86/cpufeatures: Add synthetic Secure TSC bit
To: Borislav Petkov <bp@alien8.de>
Cc: linux-kernel@vger.kernel.org, thomas.lendacky@amd.com, x86@kernel.org,
 kvm@vger.kernel.org, mingo@redhat.com, tglx@linutronix.de,
 dave.hansen@linux.intel.com, pgonda@google.com, seanjc@google.com,
 pbonzini@redhat.com
References: <20240215113128.275608-1-nikunj@amd.com>
 <20240215113128.275608-10-nikunj@amd.com>
 <20240422132521.GCZiZlQfpu1nQliyYs@fat_crate.local>
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From: "Nikunj A. Dadhania" <nikunj@amd.com>
In-Reply-To: <20240422132521.GCZiZlQfpu1nQliyYs@fat_crate.local>
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On 4/22/2024 6:55 PM, Borislav Petkov wrote:
> On Thu, Feb 15, 2024 at 05:01:21PM +0530, Nikunj A Dadhania wrote:
>> Add support for the synthetic CPUID flag which indicates that the SNP
>> guest is running with secure tsc enabled (MSR_AMD64_SEV Bit 11 -
> 
> "TSC"

Sure

> 
>> SecureTsc_Enabled) . This flag is there so that this capability in the
>> guests can be detected easily without reading MSRs every time accessors.
> 
> Why?
> 
> What's wrong with cc_platform_has(CC_ATTR_GUEST_SECURE_TSC) or so?
> 

That was the initial implementation, and there were review comments[1] to
use synthetic flag.

Regards
Nikunj

1. https://lore.kernel.org/lkml/20231106130041.gqoqszdxrmdomsxl@box.shutemov.name/