Received-SPF: pass (google.com: domain of linux-kernel+bounces-154538-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1;
Message-ID: <b9081a61-c159-4659-a5e1-5586bb65dfce@quicinc.com>
Date: Tue, 23 Apr 2024 11:41:19 +0530
Precedence: bulk
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v3 0/7] ipq9574: Enable PCI-Express support
To: <mr.nuke.me@gmail.com>, Bjorn Andersson <andersson@kernel.org>,
        Konrad
 Dybcio <konrad.dybcio@linaro.org>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>,
        Rob Herring
	<robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
        Krzysztof Kozlowski
	<krzk+dt@kernel.org>,
        Conor Dooley <conor+dt@kernel.org>, Vinod Koul
	<vkoul@kernel.org>,
        Kishon Vijay Abraham I <kishon@kernel.org>,
        Michael
 Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
        <linux-arm-msm@vger.kernel.org>, <linux-pci@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-phy@lists.infradead.org>, <linux-clk@vger.kernel.org>
References: <20240415182052.374494-1-mr.nuke.me@gmail.com>
 <4a83afeb-8e82-4f95-b44e-74d39d55f448@quicinc.com>
 <c498f5b9-df07-0802-800c-67c18dcf3e67@gmail.com>
Content-Language: en-US
From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
In-Reply-To: <c498f5b9-df07-0802-800c-67c18dcf3e67@gmail.com>
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 8bit


On 4/20/2024 1:17 AM, mr.nuke.me@gmail.com wrote:
> Hi Kathiravan,
> 
> On 4/19/24 09:28, Kathiravan Thirumoorthy wrote:
>>
>>
>> On 4/15/2024 11:50 PM, Alexandru Gagniuc wrote:
>>> There are four PCIe ports on IPQ9574, pcie0 thru pcie3. This series
>>> addresses pcie2, which is a gen3x2 port. The board I have only uses
>>> pcie2, and that's the only one enabled in this series.
>>>
>>> I believe this makes sense as a monolithic series, as the individual
>>> pieces are not that useful by themselves.
>>>
>>> In v2, I've had some issues regarding the dt schema checks. For
>>> transparency, I used the following test invocations to test v3:
>>>
>>>        make dt_binding_check 
>>> DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml
>>>        make dtbs_check 
>>> DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml
>>>
>>>
>>
>> Alexandru,
>>
>> Thanks for your contributions to the Qualcomm IPQ chipsets.
>>
>> I would like to inform you that we have also submitted the patches to 
>> enable the PCIe support on IPQ9574[1][2] and waiting for the ICC 
>> support[3] to land to enable the NOC clocks.
>>
>> [1] 
>> https://lore.kernel.org/linux-arm-msm/20230519090219.15925-1-quic_devipriy@quicinc.com/
>> [2] 
>> https://lore.kernel.org/linux-arm-msm/20230519085723.15601-1-quic_devipriy@quicinc.com/
>> [3] 
>> https://lore.kernel.org/linux-arm-msm/20240418092305.2337429-1-quic_varada@quicinc.com/
>>
>> Please take a look at these patches as well.
> 
> I think I've seen [1] before -- I thought the series was abandoned. 
> Since we have the dt-schema and applicability on mainline resolved here, 
> do you want to use this series as the base for any new PCIe work?


Sure Alex. I believe some of the code review comments are already 
addressed in the series which I pointed out. If you could have picked 
those and re-posted the next version, it could have been better.


> 
> Alex
> 
>> Thanks,
>> Kathiravan T.
>>
>>
>>> Changes since v2:
>>>   - reworked resets in qcom,pcie.yaml to resolve dt schema errors
>>>   - constrained "reg" in qcom,pcie.yaml
>>>   - reworked min/max intems in qcom,ipq8074-qmp-pcie-phy.yaml
>>>   - dropped msi-parent for pcie node, as it is handled by "msi" IRQ
>>>
>>> Changes since v1:
>>>   - updated new tables in phy-qcom-qmp-pcie.c to use lowercase hex 
>>> numbers
>>>   - reorganized qcom,ipq8074-qmp-pcie-phy.yaml to use a single list 
>>> of clocks
>>>   - reorganized qcom,pcie.yaml to include clocks+resets per compatible
>>>   - Renamed "pcie2_qmp_phy" label to "pcie2_phy"
>>>   - moved "ranges" property of pcie@20000000 higher up
>>>
>>> Alexandru Gagniuc (7):
>>>    dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574
>>>    clk: qcom: gcc-ipq9574: Add PCIe pipe clocks
>>>    dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller
>>>    PCI: qcom: Add support for IPQ9574
>>>    dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY
>>>    phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY
>>>    arm64: dts: qcom: ipq9574: add PCIe2 nodes
>>>
>>>   .../devicetree/bindings/pci/qcom,pcie.yaml    |  35 +++++
>>>   .../phy/qcom,ipq8074-qmp-pcie-phy.yaml        |  36 ++++-
>>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi         |  93 +++++++++++-
>>>   drivers/clk/qcom/gcc-ipq9574.c                |  76 ++++++++++
>>>   drivers/pci/controller/dwc/pcie-qcom.c        |  13 +-
>>>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c      | 136 +++++++++++++++++-
>>>   .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h   |  14 ++
>>>   include/dt-bindings/clock/qcom,ipq9574-gcc.h  |   4 +
>>>   8 files changed, 400 insertions(+), 7 deletions(-)
>>>