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From: Steffen Trumtrar <s.trumtrar@pengutronix.de>
To: =?utf-8?Q?S=C3=A9bastien?= Szymanski <sebastien.szymanski@armadeus.com>
Cc: "David S. Miller" <davem@davemloft.net>,  Eric Dumazet
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 <pabeni@redhat.com>,  Rob Herring <robh@kernel.org>,  Krzysztof Kozlowski
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Subject: Re: [PATCH 0/3] arm64: mx93: etherrnet: set TX_CLK in RMII mode
In-Reply-To: <f01d49cf-5955-405c-9c2b-05b0c7bb982c@armadeus.com>
 (=?utf-8?Q?=22S=C3=A9bastien?=
	Szymanski"'s message of "Mon, 22 Apr 2024 11:28:08 +0200")
References: <20240422-v6-9-topic-imx93-eqos-rmii-v1-0-30151fca43d2@pengutronix.de>
	<f01d49cf-5955-405c-9c2b-05b0c7bb982c@armadeus.com>
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Date: Tue, 23 Apr 2024 08:43:58 +0200
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Hi,

On 2024-04-22 at 11:28 +02, S=C3=A9bastien Szymanski <sebastien.szymanski@a=
rmadeus.com> wrote:=20
=20
> Hello,  On 4/22/24 10:46, Steffen Trumtrar wrote:=20
> > This series adds support for setting the TX_CLK direction in the eQOS e=
thernet core on the i.MX93 when RMII mode is used.  According to AN14149, w=
hen the i.MX93 ethernet controller is used in RMII mode, the TX_CLK *must* =
be set to output mode.=20
>  Must ? I don't think that is true. Downstream NXP kernel has an option t=
o set TX_CLK as an input:=20
>

re-reading that passage again, it only says "other registers that must be c=
onfigured" and that the ENET_QOS_CLK_TX_CLK_SEL bit "is 0b1" for RMII. So, =
maybe you are right.=20


Thanks,
Steffen

> https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/Documentation/devicetr=
ee/bindings/net/nxp%2Cdwmac-imx.yaml#L69
>=20
> https://github.com/nxp-imx/linux-imx/commit/fbc17f6f7919d03c275fc48b0400c=
212475b60ec
>=20

--=20
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