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23 Apr 2024 06:47:57 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Tue, 23 Apr 2024 16:47:53 +0300 (EEST) To: Aapo Vienamo cc: Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mika Westerberg , Andy Shevchenko Subject: Re: [PATCH] gpio: Add Intel Granite Rapids-D vGPIO driver In-Reply-To: <20240419080555.97343-1-aapo.vienamo@linux.intel.com> Message-ID: References: <20240419080555.97343-1-aapo.vienamo@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Fri, 19 Apr 2024, Aapo Vienamo wrote: > This driver provides a basic GPIO driver for the Intel Granite Rapids-D > virtual GPIOs. On SoCs with limited physical pins on the package, the > physical pins controlled by this driver would be exposed on an external > device such as a BMC or CPLD. > > Signed-off-by: Aapo Vienamo > Reviewed-by: Mika Westerberg > Signed-off-by: Andy Shevchenko > diff --git a/drivers/gpio/gpio-graniterapids.c b/drivers/gpio/gpio-graniterapids.c > new file mode 100644 > index 000000000000..61bcafe1985e > --- /dev/null > +++ b/drivers/gpio/gpio-graniterapids.c > @@ -0,0 +1,382 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Intel Granite Rapids-D vGPIO driver > + * > + * Copyright (c) 2024, Intel Corporation. > + * > + * Author: Aapo Vienamo > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#define GNR_NUM_PINS 128 > +#define GNR_PINS_PER_REG 32 > +#define GNR_NUM_REGS DIV_ROUND_UP(GNR_NUM_PINS, GNR_PINS_PER_REG) > + > +#define GNR_CFG_BAR 0x00 > +#define GNR_CFG_LOCK_OFFSET 0x04 > +#define GNR_GPI_STATUS_OFFSET 0x20 > +#define GNR_GPI_ENABLE_OFFSET 0x24 > + > +#define GNR_CFG_DW_RX_MASK (3 << 22) GENMASK() + #include > +#define GNR_CFG_DW_RX_DISABLE (2 << 22) > +#define GNR_CFG_DW_RX_EDGE (1 << 22) > +#define GNR_CFG_DW_RX_LEVEL (0 << 22) FIELD_PREP(GNR_CFG_DW_RX_MASK, xx) x 3 > +#define GNR_CFG_DW_RXDIS BIT(4) > +#define GNR_CFG_DW_TXDIS BIT(3) > +#define GNR_CFG_DW_RXSTATE BIT(1) > +#define GNR_CFG_DW_TXSTATE BIT(0) These require #include (just pointing this out so you know in future, you'll need to add it anyway for GENMASK() as mentioned above). -- i.