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AJvYcCW1R2d39jFLsGJhkaMOcMZoSt1wyAY7KY7Ku4cMi0P/YVgXYLtbCB8w5m1i4bA6PyTrNDkXPHKj/4wL+APdvxcINnzbmb0qQAG1/xgYIRQecHSh0B57DYAjWCWDPutpOSHKegANaIlRx97GcSPXyMJIPWqpz9dLYV5H/D3lCVQqedh7EKksQefWNTDy X-Gm-Message-State: AOJu0Yy3i/+oY67Vb3VjXkqnY59uegugmIRtKHSI52ms+qlCpoqJ+gHf fEA6b4C4Jpf2sUYmJTHxhvw+9s2vQm2NX8R7kDDP7FBHA15AlKid X-Received: by 2002:a05:600c:1d14:b0:419:f27f:6b05 with SMTP id l20-20020a05600c1d1400b00419f27f6b05mr30686wms.8.1713895155659; Tue, 23 Apr 2024 10:59:15 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:cef0:9ed3:1428:f85f]) by smtp.gmail.com with ESMTPSA id fl5-20020a05600c0b8500b0041abeaaf7f0sm2808145wmb.28.2024.04.23.10.59.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 10:59:14 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-renesas-soc@vger.kernel.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 00/13] Add PFC support for Renesas RZ/V2H(P) SoC Date: Tue, 23 Apr 2024 18:58:47 +0100 Message-Id: <20240423175900.702640-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Lad Prabhakar Hi All, This patch series aims to add PFC (Pin Function Controller) support for Renesas RZ/V2H(P) SoC. The PFC block on RZ/V2H(P) is almost similar to one found on the RZ/G2L family with couple of differences. To able to re-use the use the existing driver for RZ/V2H(P) SoC function pointers are introduced based on the SoC changes. RFC->v2 - Fixed review comments pointed by Rob - Incorporated changes suggested by Claudiu - Fixed build error reported for m68K - Dropped IOLH groups as we will be passing register values - Fixed configs for dedicated pins - Added support for slew-rate and bias settings - Added support for OEN RFC: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (13): dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the object dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC pinctrl: renesas: pinctrl-rzg2l: Allow more bits for pin configuration pinctrl: renesas: pinctrl-rzg2l: Allow parsing of variable configuration for all architectures pinctrl: renesas: pinctrl-rzg2l: Validate power registers for SD and ETH pinctrl: renesas: pinctrl-rzg2l: Add function pointers for locking/unlocking the PFC register pinctrl: renesas: pinctrl-rzg2l: Add function pointer for writing to PMC register pinctrl: renesas: pinctrl-rzg2l: Add function pointers for reading/writing OEN register pinctrl: renesas: pinctrl-rzg2l: Add support to configure the slew-rate pinctrl: renesas: pinctrl-rzg2l: Add support to set pulling up/down the pins pinctrl: renesas: pinctrl-rzg2l: Pass pincontrol device pointer to pinconf_generic_parse_dt_config() pinctrl: renesas: pinctrl-rzg2l: Add support for custom parameters pinctrl: renesas: pinctrl-rzg2l: Add support for RZ/V2H SoC .../pinctrl/renesas,rzg2l-pinctrl.yaml | 40 +- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 640 ++++++++++++++++-- 2 files changed, 617 insertions(+), 63 deletions(-) -- 2.34.1